Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T20,T21
1	0	Covered	T3,T8,T20

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T8,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	50487631	7943	0	0
CascadeEffAonToRstPorAboveRise_A	50487631	7943	0	0
CascadeEffAonToRstPorIoAboveFall_A	48466424	7943	0	0
CascadeEffAonToRstPorIoAboveRise_A	48466424	7943	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24234088	7943	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24234088	7943	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12116709	7943	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12116709	7943	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24234098	7943	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24234098	7943	0	0
CascadeLcToLcAboveFall_A	50487631	20972	0	0
CascadeLcToLcAboveRise_A	50487631	20972	0	0
CascadeLcToLcAonAboveFall_A	1531081	20972	0	0
CascadeLcToLcAonAboveRise_A	1531081	20972	0	0
CascadeLcToLcShadowedAboveFall_A	50487631	20972	0	0
CascadeLcToLcShadowedAboveRise_A	50487631	20972	0	0
CascadePorToAonAboveFall_A	1531081	6174	0	0
CascadeSysToSysAboveFall_A	50487631	20972	0	0
CascadeSysToSysAboveRise_A	50487631	20972	0	0
ScanRstToAonRise_A	1531081	201	0	0
StablePorToAonRise_A	1531081	7943	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10695508	20972	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10695508	20972	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10695508	20972	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10695508	20972	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12116709	20972	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12116709	20972	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10695508	20972	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10695508	20972	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10695508	20972	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10695508	20972	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	7943	0	0
T1	121687	27	0	0
T2	5228	1	0	0
T3	314769	63	0	0
T4	189167	27	0	0
T5	19320	2	0	0
T6	189123	27	0	0
T7	7740	1	0	0
T8	25940	2	0	0
T9	19644	2	0	0
T10	17064	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	7943	0	0
T1	121687	27	0	0
T2	5228	1	0	0
T3	314769	63	0	0
T4	189167	27	0	0
T5	19320	2	0	0
T6	189123	27	0	0
T7	7740	1	0	0
T8	25940	2	0	0
T9	19644	2	0	0
T10	17064	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48466424	7943	0	0
T1	116802	27	0	0
T2	5017	1	0	0
T3	302127	63	0	0
T4	181593	27	0	0
T5	18547	2	0	0
T6	181551	27	0	0
T7	7430	1	0	0
T8	24901	2	0	0
T9	18860	2	0	0
T10	16381	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48466424	7943	0	0
T1	116802	27	0	0
T2	5017	1	0	0
T3	302127	63	0	0
T4	181593	27	0	0
T5	18547	2	0	0
T6	181551	27	0	0
T7	7430	1	0	0
T8	24901	2	0	0
T9	18860	2	0	0
T10	16381	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234088	7943	0	0
T1	58402	27	0	0
T2	2509	1	0	0
T3	151098	63	0	0
T4	90787	27	0	0
T5	9273	2	0	0
T6	90784	27	0	0
T7	3714	1	0	0
T8	12452	2	0	0
T9	9430	2	0	0
T10	8189	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234088	7943	0	0
T1	58402	27	0	0
T2	2509	1	0	0
T3	151098	63	0	0
T4	90787	27	0	0
T5	9273	2	0	0
T6	90784	27	0	0
T7	3714	1	0	0
T8	12452	2	0	0
T9	9430	2	0	0
T10	8189	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	7943	0	0
T1	29205	27	0	0
T2	1252	1	0	0
T3	75541	63	0	0
T4	45398	27	0	0
T5	4635	2	0	0
T6	45393	27	0	0
T7	1857	1	0	0
T8	6226	2	0	0
T9	4715	2	0	0
T10	4094	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	7943	0	0
T1	29205	27	0	0
T2	1252	1	0	0
T3	75541	63	0	0
T4	45398	27	0	0
T5	4635	2	0	0
T6	45393	27	0	0
T7	1857	1	0	0
T8	6226	2	0	0
T9	4715	2	0	0
T10	4094	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234098	7943	0	0
T1	58412	27	0	0
T2	2508	1	0	0
T3	151078	63	0	0
T4	90788	27	0	0
T5	9273	2	0	0
T6	90769	27	0	0
T7	3714	1	0	0
T8	12449	2	0	0
T9	9428	2	0	0
T10	8190	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234098	7943	0	0
T1	58412	27	0	0
T2	2508	1	0	0
T3	151078	63	0	0
T4	90788	27	0	0
T5	9273	2	0	0
T6	90769	27	0	0
T7	3714	1	0	0
T8	12449	2	0	0
T9	9428	2	0	0
T10	8190	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	20972	0	0
T1	121687	102	0	0
T2	5228	1	0	0
T3	314769	194	0	0
T4	189167	102	0	0
T5	19320	2	0	0
T6	189123	102	0	0
T7	7740	1	0	0
T8	25940	6	0	0
T9	19644	6	0	0
T10	17064	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	20972	0	0
T1	121687	102	0	0
T2	5228	1	0	0
T3	314769	194	0	0
T4	189167	102	0	0
T5	19320	2	0	0
T6	189123	102	0	0
T7	7740	1	0	0
T8	25940	6	0	0
T9	19644	6	0	0
T10	17064	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	20972	0	0
T1	3665	102	0	0
T2	156	1	0	0
T3	9600	194	0	0
T4	5689	102	0	0
T5	579	2	0	0
T6	5688	102	0	0
T7	231	1	0	0
T8	776	6	0	0
T9	588	6	0	0
T10	511	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	20972	0	0
T1	3665	102	0	0
T2	156	1	0	0
T3	9600	194	0	0
T4	5689	102	0	0
T5	579	2	0	0
T6	5688	102	0	0
T7	231	1	0	0
T8	776	6	0	0
T9	588	6	0	0
T10	511	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	20972	0	0
T1	121687	102	0	0
T2	5228	1	0	0
T3	314769	194	0	0
T4	189167	102	0	0
T5	19320	2	0	0
T6	189123	102	0	0
T7	7740	1	0	0
T8	25940	6	0	0
T9	19644	6	0	0
T10	17064	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	20972	0	0
T1	121687	102	0	0
T2	5228	1	0	0
T3	314769	194	0	0
T4	189167	102	0	0
T5	19320	2	0	0
T6	189123	102	0	0
T7	7740	1	0	0
T8	25940	6	0	0
T9	19644	6	0	0
T10	17064	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	6174	0	0
T1	3665	27	0	0
T2	156	1	0	0
T3	9600	30	0	0
T4	5689	27	0	0
T5	579	16	0	0
T6	5688	27	0	0
T7	231	1	0	0
T8	776	1	0	0
T9	588	1	0	0
T10	511	14	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	20972	0	0
T1	121687	102	0	0
T2	5228	1	0	0
T3	314769	194	0	0
T4	189167	102	0	0
T5	19320	2	0	0
T6	189123	102	0	0
T7	7740	1	0	0
T8	25940	6	0	0
T9	19644	6	0	0
T10	17064	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50487631	20972	0	0
T1	121687	102	0	0
T2	5228	1	0	0
T3	314769	194	0	0
T4	189167	102	0	0
T5	19320	2	0	0
T6	189123	102	0	0
T7	7740	1	0	0
T8	25940	6	0	0
T9	19644	6	0	0
T10	17064	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	201	0	0
T3	9600	2	0	0
T4	5689	0	0	0
T5	579	0	0	0
T6	5688	0	0	0
T7	231	0	0	0
T8	776	0	0	0
T9	588	0	0	0
T10	511	0	0	0
T11	330	0	0	0
T13	732	0	0	0
T20	0	1	0	0
T21	0	3	0	0
T23	0	1	0	0
T47	0	3	0	0
T96	0	2	0	0
T98	0	1	0	0
T99	0	3	0	0
T100	0	1	0	0
T102	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	7943	0	0
T1	3665	27	0	0
T2	156	1	0	0
T3	9600	63	0	0
T4	5689	27	0	0
T5	579	2	0	0
T6	5688	27	0	0
T7	231	1	0	0
T8	776	2	0	0
T9	588	2	0	0
T10	511	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	20972	0	0
T1	29205	102	0	0
T2	1252	1	0	0
T3	75541	194	0	0
T4	45398	102	0	0
T5	4635	2	0	0
T6	45393	102	0	0
T7	1857	1	0	0
T8	6226	6	0	0
T9	4715	6	0	0
T10	4094	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	20972	0	0
T1	29205	102	0	0
T2	1252	1	0	0
T3	75541	194	0	0
T4	45398	102	0	0
T5	4635	2	0	0
T6	45393	102	0	0
T7	1857	1	0	0
T8	6226	6	0	0
T9	4715	6	0	0
T10	4094	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10695508	20972	0	0
T1	26023	102	0	0
T2	1211	1	0	0
T3	60997	194	0	0
T4	42338	102	0	0
T5	4498	2	0	0
T6	42063	102	0	0
T7	1838	1	0	0
T8	5986	6	0	0
T9	4425	6	0	0
T10	4028	2	0	0