Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T23,T56
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T23
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T23,T47
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T23,T47
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T23,T47
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T23,T47
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12116709	13887	0	0
gen_assertions[0].RstEnOn_A	12116709	1061	0	0
gen_assertions[0].RstNOff_A	12116709	13887	0	0
gen_assertions[0].RstNOn_A	12116709	1061	0	0
gen_assertions[1].RstEnOff_A	48466424	12683	0	0
gen_assertions[1].RstEnOn_A	48466424	991	0	0
gen_assertions[1].RstNOff_A	48466424	12683	0	0
gen_assertions[1].RstNOn_A	48466424	991	0	0
gen_assertions[2].RstEnOff_A	24234088	12722	0	0
gen_assertions[2].RstEnOn_A	24234088	969	0	0
gen_assertions[2].RstNOff_A	24234088	12722	0	0
gen_assertions[2].RstNOn_A	24234088	969	0	0
gen_assertions[3].RstEnOff_A	24234098	12795	0	0
gen_assertions[3].RstEnOn_A	24234098	1030	0	0
gen_assertions[3].RstNOff_A	24234098	12795	0	0
gen_assertions[3].RstNOn_A	24234098	1030	0	0
gen_assertions[4].RstEnOff_A	1531081	20665	0	0
gen_assertions[4].RstEnOn_A	1531081	1077	0	0
gen_assertions[4].RstNOff_A	1531081	20665	0	0
gen_assertions[4].RstNOn_A	1531081	1077	0	0
gen_assertions[5].RstEnOff_A	12116709	14115	0	0
gen_assertions[5].RstEnOn_A	12116709	1134	0	0
gen_assertions[5].RstNOff_A	12116709	14115	0	0
gen_assertions[5].RstNOn_A	12116709	1134	0	0
gen_assertions[6].RstEnOff_A	12116709	14188	0	0
gen_assertions[6].RstEnOn_A	12116709	1200	0	0
gen_assertions[6].RstNOff_A	12116709	14188	0	0
gen_assertions[6].RstNOn_A	12116709	1200	0	0
gen_assertions[7].RstEnOff_A	12116709	14214	0	0
gen_assertions[7].RstEnOn_A	12116709	1225	0	0
gen_assertions[7].RstNOff_A	12116709	14214	0	0
gen_assertions[7].RstNOn_A	12116709	1225	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	13887	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	138	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	5	0	0
T9	4715	5	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1061	0	0
T3	75541	8	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	1	0	0
T9	4715	1	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	10	0	0
T38	0	8	0	0
T47	0	11	0	0
T50	0	6	0	0
T56	0	1	0	0
T57	0	3	0	0
T90	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	13887	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	138	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	5	0	0
T9	4715	5	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1061	0	0
T3	75541	8	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	1	0	0
T9	4715	1	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	10	0	0
T38	0	8	0	0
T47	0	11	0	0
T50	0	6	0	0
T56	0	1	0	0
T57	0	3	0	0
T90	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48466424	12683	0	0
T1	116802	65	0	0
T2	5017	0	0	0
T3	302127	122	0	0
T4	181593	67	0	0
T5	18547	0	0	0
T6	181551	63	0	0
T7	7430	0	0	0
T8	24901	4	0	0
T9	18860	4	0	0
T10	16381	0	0	0
T20	0	28	0	0
T21	0	32	0	0
T22	0	4	0	0
T23	0	89	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48466424	991	0	0
T3	302127	6	0	0
T4	181593	0	0	0
T5	18547	0	0	0
T6	181551	0	0	0
T7	7430	0	0	0
T8	24901	0	0	0
T9	18860	0	0	0
T10	16381	0	0	0
T11	10606	0	0	0
T13	23382	0	0	0
T23	0	9	0	0
T38	0	6	0	0
T40	0	1	0	0
T47	0	11	0	0
T50	0	8	0	0
T51	0	5	0	0
T52	0	8	0	0
T56	0	1	0	0
T91	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48466424	12683	0	0
T1	116802	65	0	0
T2	5017	0	0	0
T3	302127	122	0	0
T4	181593	67	0	0
T5	18547	0	0	0
T6	181551	63	0	0
T7	7430	0	0	0
T8	24901	4	0	0
T9	18860	4	0	0
T10	16381	0	0	0
T20	0	28	0	0
T21	0	32	0	0
T22	0	4	0	0
T23	0	89	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48466424	991	0	0
T3	302127	6	0	0
T4	181593	0	0	0
T5	18547	0	0	0
T6	181551	0	0	0
T7	7430	0	0	0
T8	24901	0	0	0
T9	18860	0	0	0
T10	16381	0	0	0
T11	10606	0	0	0
T13	23382	0	0	0
T23	0	9	0	0
T38	0	6	0	0
T40	0	1	0	0
T47	0	11	0	0
T50	0	8	0	0
T51	0	5	0	0
T52	0	8	0	0
T56	0	1	0	0
T91	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234088	12722	0	0
T1	58402	65	0	0
T2	2509	0	0	0
T3	151098	123	0	0
T4	90787	67	0	0
T5	9273	0	0	0
T6	90784	63	0	0
T7	3714	0	0	0
T8	12452	5	0	0
T9	9430	5	0	0
T10	8189	0	0	0
T20	0	28	0	0
T21	0	32	0	0
T22	0	4	0	0
T23	0	90	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234088	969	0	0
T3	151098	7	0	0
T4	90787	0	0	0
T5	9273	0	0	0
T6	90784	0	0	0
T7	3714	0	0	0
T8	12452	1	0	0
T9	9430	1	0	0
T10	8189	0	0	0
T11	5302	0	0	0
T13	11688	0	0	0
T23	0	10	0	0
T47	0	10	0	0
T50	0	9	0	0
T51	0	6	0	0
T52	0	9	0	0
T92	0	1	0	0
T93	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234088	12722	0	0
T1	58402	65	0	0
T2	2509	0	0	0
T3	151098	123	0	0
T4	90787	67	0	0
T5	9273	0	0	0
T6	90784	63	0	0
T7	3714	0	0	0
T8	12452	5	0	0
T9	9430	5	0	0
T10	8189	0	0	0
T20	0	28	0	0
T21	0	32	0	0
T22	0	4	0	0
T23	0	90	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234088	969	0	0
T3	151098	7	0	0
T4	90787	0	0	0
T5	9273	0	0	0
T6	90784	0	0	0
T7	3714	0	0	0
T8	12452	1	0	0
T9	9430	1	0	0
T10	8189	0	0	0
T11	5302	0	0	0
T13	11688	0	0	0
T23	0	10	0	0
T47	0	10	0	0
T50	0	9	0	0
T51	0	6	0	0
T52	0	9	0	0
T92	0	1	0	0
T93	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234098	12795	0	0
T1	58412	65	0	0
T2	2508	0	0	0
T3	151078	123	0	0
T4	90788	67	0	0
T5	9273	0	0	0
T6	90769	63	0	0
T7	3714	0	0	0
T8	12449	5	0	0
T9	9428	4	0	0
T10	8190	0	0	0
T20	0	28	0	0
T21	0	32	0	0
T22	0	4	0	0
T23	0	90	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234098	1030	0	0
T3	151078	6	0	0
T4	90788	0	0	0
T5	9273	0	0	0
T6	90769	0	0	0
T7	3714	0	0	0
T8	12449	1	0	0
T9	9428	0	0	0
T10	8190	0	0	0
T11	5301	0	0	0
T13	11690	0	0	0
T23	0	9	0	0
T47	0	7	0	0
T50	0	10	0	0
T51	0	9	0	0
T52	0	8	0	0
T93	0	6	0	0
T94	0	1	0	0
T95	0	1	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234098	12795	0	0
T1	58412	65	0	0
T2	2508	0	0	0
T3	151078	123	0	0
T4	90788	67	0	0
T5	9273	0	0	0
T6	90769	63	0	0
T7	3714	0	0	0
T8	12449	5	0	0
T9	9428	4	0	0
T10	8190	0	0	0
T20	0	28	0	0
T21	0	32	0	0
T22	0	4	0	0
T23	0	90	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24234098	1030	0	0
T3	151078	6	0	0
T4	90788	0	0	0
T5	9273	0	0	0
T6	90769	0	0	0
T7	3714	0	0	0
T8	12449	1	0	0
T9	9428	0	0	0
T10	8190	0	0	0
T11	5301	0	0	0
T13	11690	0	0	0
T23	0	9	0	0
T47	0	7	0	0
T50	0	10	0	0
T51	0	9	0	0
T52	0	8	0	0
T93	0	6	0	0
T94	0	1	0	0
T95	0	1	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	20665	0	0
T1	3665	76	0	0
T2	156	1	0	0
T3	9600	196	0	0
T4	5689	89	0	0
T5	579	2	0	0
T6	5688	87	0	0
T7	231	1	0	0
T8	776	6	0	0
T9	588	6	0	0
T10	511	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	1077	0	0
T3	9600	10	0	0
T4	5689	0	0	0
T5	579	0	0	0
T6	5688	0	0	0
T7	231	0	0	0
T8	776	0	0	0
T9	588	0	0	0
T10	511	0	0	0
T11	330	0	0	0
T13	732	0	0	0
T23	0	9	0	0
T47	0	11	0	0
T50	0	12	0	0
T51	0	9	0	0
T52	0	6	0	0
T93	0	5	0	0
T94	0	1	0	0
T96	0	13	0	0
T97	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	20665	0	0
T1	3665	76	0	0
T2	156	1	0	0
T3	9600	196	0	0
T4	5689	89	0	0
T5	579	2	0	0
T6	5688	87	0	0
T7	231	1	0	0
T8	776	6	0	0
T9	588	6	0	0
T10	511	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1531081	1077	0	0
T3	9600	10	0	0
T4	5689	0	0	0
T5	579	0	0	0
T6	5688	0	0	0
T7	231	0	0	0
T8	776	0	0	0
T9	588	0	0	0
T10	511	0	0	0
T11	330	0	0	0
T13	732	0	0	0
T23	0	9	0	0
T47	0	11	0	0
T50	0	12	0	0
T51	0	9	0	0
T52	0	6	0	0
T93	0	5	0	0
T94	0	1	0	0
T96	0	13	0	0
T97	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	14115	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	139	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	4	0	0
T9	4715	4	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1134	0	0
T3	75541	9	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	0	0	0
T9	4715	0	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	10	0	0
T40	0	1	0	0
T47	0	9	0	0
T50	0	12	0	0
T51	0	10	0	0
T52	0	10	0	0
T90	0	1	0	0
T93	0	7	0	0
T98	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	14115	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	139	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	4	0	0
T9	4715	4	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1134	0	0
T3	75541	9	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	0	0	0
T9	4715	0	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	10	0	0
T40	0	1	0	0
T47	0	9	0	0
T50	0	12	0	0
T51	0	10	0	0
T52	0	10	0	0
T90	0	1	0	0
T93	0	7	0	0
T98	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	14188	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	140	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	4	0	0
T9	4715	4	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1200	0	0
T3	75541	11	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	0	0	0
T9	4715	0	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	9	0	0
T47	0	11	0	0
T50	0	11	0	0
T51	0	12	0	0
T52	0	12	0	0
T93	0	8	0	0
T96	0	18	0	0
T97	0	12	0	0
T99	0	39	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	14188	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	140	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	4	0	0
T9	4715	4	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1200	0	0
T3	75541	11	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	0	0	0
T9	4715	0	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	9	0	0
T47	0	11	0	0
T50	0	11	0	0
T51	0	12	0	0
T52	0	12	0	0
T93	0	8	0	0
T96	0	18	0	0
T97	0	12	0	0
T99	0	39	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	14214	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	138	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	4	0	0
T9	4715	4	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1225	0	0
T3	75541	9	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	0	0	0
T9	4715	0	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	9	0	0
T47	0	12	0	0
T50	0	14	0	0
T51	0	13	0	0
T52	0	13	0	0
T93	0	11	0	0
T96	0	17	0	0
T97	0	11	0	0
T99	0	39	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	14214	0	0
T1	29205	75	0	0
T2	1252	0	0	0
T3	75541	138	0	0
T4	45398	75	0	0
T5	4635	0	0	0
T6	45393	75	0	0
T7	1857	0	0	0
T8	6226	4	0	0
T9	4715	4	0	0
T10	4094	0	0	0
T20	0	30	0	0
T21	0	36	0	0
T22	0	4	0	0
T23	0	99	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12116709	1225	0	0
T3	75541	9	0	0
T4	45398	0	0	0
T5	4635	0	0	0
T6	45393	0	0	0
T7	1857	0	0	0
T8	6226	0	0	0
T9	4715	0	0	0
T10	4094	0	0	0
T11	2650	0	0	0
T13	5844	0	0	0
T23	0	9	0	0
T47	0	12	0	0
T50	0	14	0	0
T51	0	13	0	0
T52	0	13	0	0
T93	0	11	0	0
T96	0	17	0	0
T97	0	11	0	0
T99	0	39	0	0