Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11496400	7656	0	0
alert_regwen_rd_A	11496400	5539	0	0
cpu_regwen_rd_A	11496400	5499	0	0
sw_rst_ctrl_n_0_rd_A	11496400	10971	0	0
sw_rst_ctrl_n_1_rd_A	11496400	10704	0	0
sw_rst_ctrl_n_2_rd_A	11496400	10605	0	0
sw_rst_ctrl_n_3_rd_A	11496400	10975	0	0
sw_rst_ctrl_n_4_rd_A	11496400	10818	0	0
sw_rst_ctrl_n_5_rd_A	11496400	10976	0	0
sw_rst_ctrl_n_6_rd_A	11496400	10811	0	0
sw_rst_ctrl_n_7_rd_A	11496400	10642	0	0
sw_rst_regwen_0_rd_A	11496400	6057	0	0
sw_rst_regwen_1_rd_A	11496400	6060	0	0
sw_rst_regwen_2_rd_A	11496400	6225	0	0
sw_rst_regwen_3_rd_A	11496400	6126	0	0
sw_rst_regwen_4_rd_A	11496400	6125	0	0
sw_rst_regwen_5_rd_A	11496400	5905	0	0
sw_rst_regwen_6_rd_A	11496400	6096	0	0
sw_rst_regwen_7_rd_A	11496400	6295	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	7656	0	0
T54	4735	19	0	0
T58	4325	427	0	0
T59	3292	17	0	0
T60	7114	142	0	0
T74	19894	4	0	0
T76	12156	514	0	0
T77	5248	191	0	0
T80	2082	17	0	0
T86	3182	8	0	0
T88	2761	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	5539	0	0
T14	2166	0	0	0
T23	97029	142	0	0
T46	1586	0	0	0
T47	91674	171	0	0
T49	4549	0	0	0
T56	4498	0	0	0
T57	3813	0	0	0
T71	0	96	0	0
T99	0	312	0	0
T102	0	31	0	0
T116	0	234	0	0
T117	0	76	0	0
T118	0	378	0	0
T119	0	35	0	0
T120	0	344	0	0
T121	1962	0	0	0
T122	41785	0	0	0
T123	2090	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	5499	0	0
T14	2166	0	0	0
T23	97029	112	0	0
T46	1586	0	0	0
T47	91674	172	0	0
T49	4549	0	0	0
T56	4498	0	0	0
T57	3813	0	0	0
T71	0	110	0	0
T99	0	301	0	0
T102	0	41	0	0
T116	0	261	0	0
T117	0	70	0	0
T118	0	433	0	0
T119	0	9	0	0
T120	0	312	0	0
T121	1962	0	0	0
T122	41785	0	0	0
T123	2090	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10971	0	0
T8	5986	20	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	241	0	0
T40	0	4	0	0
T47	0	259	0	0
T50	0	202	0	0
T52	0	168	0	0
T93	0	151	0	0
T97	0	199	0	0
T102	0	32	0	0
T124	0	18	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10704	0	0
T8	5986	6	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	254	0	0
T40	0	9	0	0
T47	0	293	0	0
T50	0	202	0	0
T52	0	177	0	0
T93	0	144	0	0
T97	0	140	0	0
T102	0	43	0	0
T124	0	6	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10605	0	0
T8	5986	10	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	245	0	0
T40	0	13	0	0
T47	0	277	0	0
T50	0	248	0	0
T52	0	206	0	0
T93	0	154	0	0
T97	0	192	0	0
T102	0	36	0	0
T124	0	19	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10975	0	0
T8	5986	11	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	220	0	0
T40	0	18	0	0
T47	0	287	0	0
T50	0	175	0	0
T52	0	208	0	0
T93	0	156	0	0
T97	0	191	0	0
T102	0	46	0	0
T124	0	12	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10818	0	0
T8	5986	9	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	251	0	0
T40	0	7	0	0
T47	0	302	0	0
T50	0	234	0	0
T52	0	167	0	0
T93	0	136	0	0
T97	0	170	0	0
T102	0	36	0	0
T124	0	9	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10976	0	0
T8	5986	17	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	198	0	0
T40	0	6	0	0
T47	0	268	0	0
T50	0	203	0	0
T52	0	175	0	0
T93	0	143	0	0
T97	0	205	0	0
T102	0	46	0	0
T124	0	23	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10811	0	0
T8	5986	14	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	254	0	0
T40	0	3	0	0
T47	0	300	0	0
T50	0	233	0	0
T52	0	182	0	0
T93	0	156	0	0
T97	0	217	0	0
T102	0	39	0	0
T124	0	20	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	10642	0	0
T8	5986	13	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	254	0	0
T40	0	15	0	0
T47	0	240	0	0
T50	0	205	0	0
T52	0	133	0	0
T93	0	156	0	0
T97	0	163	0	0
T102	0	52	0	0
T124	0	13	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	6057	0	0
T8	5986	1	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	138	0	0
T40	0	6	0	0
T47	0	169	0	0
T50	0	36	0	0
T52	0	24	0	0
T93	0	24	0	0
T97	0	17	0	0
T99	0	283	0	0
T102	0	72	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	6060	0	0
T8	5986	3	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	135	0	0
T40	0	6	0	0
T47	0	132	0	0
T50	0	32	0	0
T52	0	46	0	0
T93	0	17	0	0
T97	0	35	0	0
T99	0	306	0	0
T102	0	41	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	6225	0	0
T8	5986	12	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	109	0	0
T40	0	6	0	0
T47	0	161	0	0
T50	0	38	0	0
T52	0	17	0	0
T93	0	27	0	0
T97	0	37	0	0
T99	0	338	0	0
T102	0	41	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	6126	0	0
T8	5986	4	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	98	0	0
T40	0	6	0	0
T47	0	157	0	0
T50	0	15	0	0
T52	0	36	0	0
T93	0	37	0	0
T97	0	38	0	0
T99	0	315	0	0
T102	0	33	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	6125	0	0
T8	5986	3	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	139	0	0
T40	0	9	0	0
T47	0	156	0	0
T50	0	55	0	0
T52	0	32	0	0
T93	0	36	0	0
T97	0	26	0	0
T99	0	368	0	0
T102	0	40	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	5905	0	0
T8	5986	2	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	141	0	0
T40	0	3	0	0
T47	0	168	0	0
T50	0	36	0	0
T52	0	29	0	0
T93	0	41	0	0
T97	0	45	0	0
T99	0	277	0	0
T102	0	45	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	6096	0	0
T8	5986	4	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	143	0	0
T40	0	10	0	0
T47	0	152	0	0
T50	0	36	0	0
T52	0	42	0	0
T93	0	35	0	0
T97	0	39	0	0
T99	0	322	0	0
T102	0	45	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11496400	6295	0	0
T8	5986	6	0	0
T9	4425	0	0	0
T10	4028	0	0	0
T11	2536	0	0	0
T12	3111	0	0	0
T13	5492	0	0	0
T20	23388	0	0	0
T21	19930	0	0	0
T22	3131	0	0	0
T23	97029	126	0	0
T40	0	7	0	0
T47	0	163	0	0
T50	0	30	0	0
T52	0	29	0	0
T93	0	29	0	0
T97	0	53	0	0
T99	0	347	0	0
T102	0	36	0	0