Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	607999	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

364225

1

T1

65

T3

128

T4

63

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	517794	1			T1	99		T2	1		T3	178
values[0x0]	226711	1			T1	56		T3	99		T4	54
values[0x1]	227719	1			T1	57		T3	90		T4	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	510264	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

461960

1

T1

93

T2

1

T3

170

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4174	1			T4	16		T6	13		T8	82
valid_sources[0x01]	3615	1			T1	5		T6	7		T8	54
valid_sources[0x02]	3211	1			T1	1		T6	27		T8	56
valid_sources[0x03]	3075	1			T6	12		T8	49		T9	42
valid_sources[0x04]	3342	1			T6	7		T8	83		T9	36
valid_sources[0x05]	3672	1			T6	5		T8	74		T9	37
valid_sources[0x06]	3273	1			T1	2		T6	9		T8	33
valid_sources[0x07]	3350	1			T6	18		T8	85		T9	34
valid_sources[0x08]	3146	1			T1	1		T8	39		T9	41
valid_sources[0x09]	3331	1			T1	1		T8	43		T9	34
valid_sources[0x0a]	4235	1			T6	12		T8	34		T9	45
valid_sources[0x0b]	3607	1			T6	11		T8	24		T9	32
valid_sources[0x0c]	3879	1			T6	3		T8	56		T9	41
valid_sources[0x0d]	3108	1			T4	9		T6	5		T8	90
valid_sources[0x0e]	3324	1			T6	11		T8	55		T9	45
valid_sources[0x0f]	3680	1			T6	1		T8	29		T9	50
valid_sources[0x10]	4929	1			T6	11		T8	70		T9	50
valid_sources[0x11]	4507	1			T6	3		T8	37		T9	49
valid_sources[0x12]	3322	1			T6	22		T8	98		T9	54
valid_sources[0x13]	3275	1			T6	10		T8	24		T9	41
valid_sources[0x14]	3279	1			T6	22		T8	49		T9	47
valid_sources[0x15]	3745	1			T1	2		T6	22		T8	35
valid_sources[0x16]	4415	1			T6	6		T8	64		T9	49
valid_sources[0x17]	3749	1			T1	2		T6	2		T8	18
valid_sources[0x18]	4969	1			T6	3		T8	18		T9	40
valid_sources[0x19]	4442	1			T6	5		T8	68		T9	36
valid_sources[0x1a]	3389	1			T1	1		T6	3		T8	112
valid_sources[0x1b]	3207	1			T6	17		T8	12		T9	48
valid_sources[0x1c]	3533	1			T6	8		T8	51		T9	31
valid_sources[0x1d]	3880	1			T4	4		T6	11		T8	64
valid_sources[0x1e]	3375	1			T6	12		T8	40		T9	38
valid_sources[0x1f]	3811	1			T4	1		T6	23		T8	27
valid_sources[0x20]	3179	1			T6	20		T8	27		T9	40
valid_sources[0x21]	3520	1			T1	4		T6	18		T8	65
valid_sources[0x22]	2995	1			T8	45		T9	37		T10	103
valid_sources[0x23]	3612	1			T1	3		T6	6		T8	45
valid_sources[0x24]	3447	1			T1	2		T4	3		T6	18
valid_sources[0x25]	3727	1			T4	12		T6	11		T8	47
valid_sources[0x26]	3214	1			T4	4		T6	12		T8	29
valid_sources[0x27]	3976	1			T1	1		T6	7		T8	86
valid_sources[0x28]	3202	1			T1	7		T4	2		T6	14
valid_sources[0x29]	7199	1			T1	11		T6	19		T8	12
valid_sources[0x2a]	3494	1			T1	1		T4	2		T6	23
valid_sources[0x2b]	4379	1			T1	5		T6	3		T8	27
valid_sources[0x2c]	3453	1			T6	9		T8	68		T9	42
valid_sources[0x2d]	3410	1			T4	1		T6	23		T8	41
valid_sources[0x2e]	3884	1			T6	4		T8	52		T9	34
valid_sources[0x2f]	3199	1			T6	2		T8	50		T9	34
valid_sources[0x30]	3831	1			T6	5		T8	94		T9	42
valid_sources[0x31]	3797	1			T6	1		T8	51		T9	65
valid_sources[0x32]	7101	1			T1	4		T6	9		T7	3200
valid_sources[0x33]	3914	1			T6	10		T8	30		T9	49
valid_sources[0x34]	3476	1			T6	3		T8	49		T9	43
valid_sources[0x35]	3673	1			T4	5		T6	10		T8	40
valid_sources[0x36]	4023	1			T1	2		T4	2		T6	14
valid_sources[0x37]	3080	1			T6	19		T8	76		T9	41
valid_sources[0x38]	3823	1			T6	6		T8	33		T9	27
valid_sources[0x39]	3755	1			T6	1		T8	83		T9	39
valid_sources[0x3a]	4117	1			T6	6		T8	42		T9	42
valid_sources[0x3b]	3482	1			T6	10		T8	38		T9	38
valid_sources[0x3c]	3393	1			T4	7		T6	23		T8	60
valid_sources[0x3d]	4233	1			T6	30		T8	30		T9	38
valid_sources[0x3e]	3686	1			T1	13		T6	10		T8	23
valid_sources[0x3f]	3285	1			T6	19		T8	53		T9	47
valid_sources[0x40]	3708	1			T6	11		T8	23		T9	30
valid_sources[0x41]	3473	1			T6	3		T8	53		T9	31
valid_sources[0x42]	3363	1			T1	2		T8	28		T9	30
valid_sources[0x43]	3551	1			T6	14		T8	36		T9	30
valid_sources[0x44]	3526	1			T1	4		T6	2		T8	51
valid_sources[0x45]	2823	1			T1	3		T6	13		T8	61
valid_sources[0x46]	3123	1			T4	5		T6	10		T8	47
valid_sources[0x47]	3979	1			T6	7		T8	30		T9	54
valid_sources[0x48]	3142	1			T8	103		T9	28		T10	77
valid_sources[0x49]	4331	1			T6	10		T8	55		T9	41
valid_sources[0x4a]	3481	1			T6	1		T8	72		T9	47
valid_sources[0x4b]	3299	1			T6	10		T8	56		T9	45
valid_sources[0x4c]	3972	1			T1	9		T6	7		T8	51
valid_sources[0x4d]	3999	1			T6	7		T8	76		T9	26
valid_sources[0x4e]	3753	1			T6	5		T8	24		T9	39
valid_sources[0x4f]	3788	1			T6	5		T8	53		T9	36
valid_sources[0x50]	3139	1			T6	6		T8	18		T9	44
valid_sources[0x51]	3720	1			T6	18		T8	89		T9	35
valid_sources[0x52]	3181	1			T6	10		T8	23		T9	38
valid_sources[0x53]	3873	1			T1	3		T6	7		T8	61
valid_sources[0x54]	4186	1			T6	4		T8	81		T9	46
valid_sources[0x55]	3651	1			T6	6		T8	11		T9	36
valid_sources[0x56]	3743	1			T6	7		T8	64		T9	26
valid_sources[0x57]	3511	1			T1	8		T6	2		T8	66
valid_sources[0x58]	4226	1			T4	1		T6	1		T8	71
valid_sources[0x59]	3411	1			T1	1		T6	18		T8	49
valid_sources[0x5a]	3183	1			T6	5		T8	25		T9	31
valid_sources[0x5b]	3022	1			T1	1		T4	2		T6	14
valid_sources[0x5c]	7337	1			T6	19		T8	32		T9	53
valid_sources[0x5d]	4195	1			T1	4		T6	8		T8	30
valid_sources[0x5e]	3734	1			T6	15		T8	44		T9	55
valid_sources[0x5f]	3749	1			T6	14		T8	108		T9	40
valid_sources[0x60]	4557	1			T6	11		T8	38		T9	32
valid_sources[0x61]	3261	1			T6	1		T8	25		T9	46
valid_sources[0x62]	3150	1			T6	20		T8	45		T9	44
valid_sources[0x63]	3012	1			T6	7		T8	54		T9	49
valid_sources[0x64]	3164	1			T1	4		T6	16		T8	51
valid_sources[0x65]	3479	1			T1	5		T6	11		T8	30
valid_sources[0x66]	5099	1			T4	5		T6	23		T8	94
valid_sources[0x67]	3297	1			T1	1		T6	3		T8	27
valid_sources[0x68]	3769	1			T5	6		T6	4		T8	24
valid_sources[0x69]	2850	1			T1	1		T4	8		T6	6
valid_sources[0x6a]	4168	1			T6	16		T8	74		T9	28
valid_sources[0x6b]	3701	1			T6	14		T8	65		T9	44
valid_sources[0x6c]	4125	1			T6	4		T8	37		T9	53
valid_sources[0x6d]	3551	1			T1	5		T6	3		T8	23
valid_sources[0x6e]	3769	1			T1	1		T6	10		T8	66
valid_sources[0x6f]	3471	1			T6	11		T8	67		T9	33
valid_sources[0x70]	4390	1			T6	3		T8	10		T9	48
valid_sources[0x71]	4123	1			T6	15		T8	30		T9	31
valid_sources[0x72]	3337	1			T6	9		T8	72		T9	45
valid_sources[0x73]	4218	1			T4	2		T6	18		T8	36
valid_sources[0x74]	3999	1			T1	1		T6	23		T8	37
valid_sources[0x75]	3679	1			T6	7		T8	26		T9	52
valid_sources[0x76]	3415	1			T6	22		T8	67		T9	45
valid_sources[0x77]	3931	1			T6	22		T8	52		T9	39
valid_sources[0x78]	3244	1			T6	7		T8	76		T9	48
valid_sources[0x79]	3105	1			T4	3		T6	6		T8	81
valid_sources[0x7a]	3452	1			T1	3		T6	20		T8	66
valid_sources[0x7b]	3353	1			T1	3		T6	6		T8	38
valid_sources[0x7c]	4577	1			T6	21		T8	54		T9	38
valid_sources[0x7d]	3232	1			T8	61		T9	39		T10	81
valid_sources[0x7e]	3627	1			T4	2		T6	4		T8	39
valid_sources[0x7f]	3983	1			T6	12		T8	21		T9	32
valid_sources[0x80]	3003	1			T6	11		T8	60		T9	42

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241934

1

T1

42

T3

78

T4

41

values[0x0]

all_enables

biggest_size

79696

1

T1

12

T3

32

T4

15

values[0x1]

all_enables

biggest_size

42595

1

T1

11

T3

18

T4

7