Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11074966	13005	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11074966	120047	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11074966	6459545	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11074966	191772	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11074966	13005	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11074966	120047	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11074966	6459545	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11074966	191772	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	13005	0	0
T1	3855	4	0	0
T2	4622	0	0	0
T3	2730	18	0	0
T4	2376	4	0	0
T5	1489	0	0	0
T6	17802	34	0	0
T7	26265	75	0	0
T8	83995	187	0	0
T9	64519	125	0	0
T10	229072	243	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	120047	0	0
T1	3855	38	0	0
T2	4622	0	0	0
T3	2730	162	0	0
T4	2376	38	0	0
T5	1489	0	0	0
T6	17802	309	0	0
T7	26265	710	0	0
T8	83995	1694	0	0
T9	64519	1131	0	0
T10	229072	2237	0	0
T20	0	262	0	0
T21	0	37	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	6459545	0	0
T1	3855	2907	0	0
T2	4622	776	0	0
T3	2730	1875	0	0
T4	2376	1367	0	0
T5	1489	876	0	0
T6	17802	7826	0	0
T7	26265	8736	0	0
T8	83995	42236	0	0
T9	64519	34200	0	0
T10	229072	165884	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	191772	0	0
T1	3855	73	0	0
T2	4622	0	0	0
T3	2730	252	0	0
T4	2376	58	0	0
T5	1489	0	0	0
T6	17802	499	0	0
T7	26265	1167	0	0
T8	83995	2812	0	0
T9	64519	1808	0	0
T10	229072	3586	0	0
T20	0	434	0	0
T21	0	69	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	13005	0	0
T1	3855	4	0	0
T2	4622	0	0	0
T3	2730	18	0	0
T4	2376	4	0	0
T5	1489	0	0	0
T6	17802	34	0	0
T7	26265	75	0	0
T8	83995	187	0	0
T9	64519	125	0	0
T10	229072	243	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	120047	0	0
T1	3855	38	0	0
T2	4622	0	0	0
T3	2730	162	0	0
T4	2376	38	0	0
T5	1489	0	0	0
T6	17802	309	0	0
T7	26265	710	0	0
T8	83995	1694	0	0
T9	64519	1131	0	0
T10	229072	2237	0	0
T20	0	262	0	0
T21	0	37	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	6459545	0	0
T1	3855	2907	0	0
T2	4622	776	0	0
T3	2730	1875	0	0
T4	2376	1367	0	0
T5	1489	876	0	0
T6	17802	7826	0	0
T7	26265	8736	0	0
T8	83995	42236	0	0
T9	64519	34200	0	0
T10	229072	165884	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	191772	0	0
T1	3855	73	0	0
T2	4622	0	0	0
T3	2730	252	0	0
T4	2376	58	0	0
T5	1489	0	0	0
T6	17802	499	0	0
T7	26265	1167	0	0
T8	83995	2812	0	0
T9	64519	1808	0	0
T10	229072	3586	0	0
T20	0	434	0	0
T21	0	69	0	0