Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T6,T8
1	0	Covered	T6,T8,T9

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52249860	8522	0	0
CascadeEffAonToRstPorAboveRise_A	52249860	8522	0	0
CascadeEffAonToRstPorIoAboveFall_A	50158224	8522	0	0
CascadeEffAonToRstPorIoAboveRise_A	50158224	8522	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25079962	8522	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25079962	8522	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12539684	8522	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12539684	8522	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25080026	8522	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25080026	8522	0	0
CascadeLcToLcAboveFall_A	52249860	21527	0	0
CascadeLcToLcAboveRise_A	52249860	21527	0	0
CascadeLcToLcAonAboveFall_A	1583700	21527	0	0
CascadeLcToLcAonAboveRise_A	1583700	21527	0	0
CascadeLcToLcShadowedAboveFall_A	52249860	21527	0	0
CascadeLcToLcShadowedAboveRise_A	52249860	21527	0	0
CascadePorToAonAboveFall_A	1583700	6797	0	0
CascadeSysToSysAboveFall_A	52249860	21527	0	0
CascadeSysToSysAboveRise_A	52249860	21527	0	0
ScanRstToAonRise_A	1583700	218	0	0
StablePorToAonRise_A	1583700	8522	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11074966	21527	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11074966	21527	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11074966	21527	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11074966	21527	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12539684	21527	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12539684	21527	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11074966	21527	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11074966	21527	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11074966	21527	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11074966	21527	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	8522	0	0
T1	17279	2	0	0
T2	19741	2	0	0
T3	16458	1	0	0
T4	10286	2	0	0
T5	6386	1	0	0
T6	95399	20	0	0
T7	122082	27	0	0
T8	448815	91	0	0
T9	336976	65	0	0
T10	108699	139	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	8522	0	0
T1	17279	2	0	0
T2	19741	2	0	0
T3	16458	1	0	0
T4	10286	2	0	0
T5	6386	1	0	0
T6	95399	20	0	0
T7	122082	27	0	0
T8	448815	91	0	0
T9	336976	65	0	0
T10	108699	139	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50158224	8522	0	0
T1	16585	2	0	0
T2	18951	2	0	0
T3	15798	1	0	0
T4	9875	2	0	0
T5	6130	1	0	0
T6	91618	20	0	0
T7	117215	27	0	0
T8	430825	91	0	0
T9	323525	65	0	0
T10	104347	139	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50158224	8522	0	0
T1	16585	2	0	0
T2	18951	2	0	0
T3	15798	1	0	0
T4	9875	2	0	0
T5	6130	1	0	0
T6	91618	20	0	0
T7	117215	27	0	0
T8	430825	91	0	0
T9	323525	65	0	0
T10	104347	139	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25079962	8522	0	0
T1	8292	2	0	0
T2	9475	2	0	0
T3	7899	1	0	0
T4	4939	2	0	0
T5	3064	1	0	0
T6	45801	20	0	0
T7	58599	27	0	0
T8	215420	91	0	0
T9	161776	65	0	0
T10	521770	139	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25079962	8522	0	0
T1	8292	2	0	0
T2	9475	2	0	0
T3	7899	1	0	0
T4	4939	2	0	0
T5	3064	1	0	0
T6	45801	20	0	0
T7	58599	27	0	0
T8	215420	91	0	0
T9	161776	65	0	0
T10	521770	139	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	8522	0	0
T1	4147	2	0	0
T2	4736	2	0	0
T3	3948	1	0	0
T4	2468	2	0	0
T5	1531	1	0	0
T6	22897	20	0	0
T7	29304	27	0	0
T8	107707	91	0	0
T9	80898	65	0	0
T10	260901	139	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	8522	0	0
T1	4147	2	0	0
T2	4736	2	0	0
T3	3948	1	0	0
T4	2468	2	0	0
T5	1531	1	0	0
T6	22897	20	0	0
T7	29304	27	0	0
T8	107707	91	0	0
T9	80898	65	0	0
T10	260901	139	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25080026	8522	0	0
T1	8292	2	0	0
T2	9476	2	0	0
T3	7899	1	0	0
T4	4940	2	0	0
T5	3064	1	0	0
T6	45795	20	0	0
T7	58626	27	0	0
T8	215424	91	0	0
T9	161778	65	0	0
T10	521781	139	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25080026	8522	0	0
T1	8292	2	0	0
T2	9476	2	0	0
T3	7899	1	0	0
T4	4940	2	0	0
T5	3064	1	0	0
T6	45795	20	0	0
T7	58626	27	0	0
T8	215424	91	0	0
T9	161778	65	0	0
T10	521781	139	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	21527	0	0
T1	17279	6	0	0
T2	19741	2	0	0
T3	16458	19	0	0
T4	10286	6	0	0
T5	6386	1	0	0
T6	95399	54	0	0
T7	122082	102	0	0
T8	448815	278	0	0
T9	336976	190	0	0
T10	108699	382	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	21527	0	0
T1	17279	6	0	0
T2	19741	2	0	0
T3	16458	19	0	0
T4	10286	6	0	0
T5	6386	1	0	0
T6	95399	54	0	0
T7	122082	102	0	0
T8	448815	278	0	0
T9	336976	190	0	0
T10	108699	382	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	21527	0	0
T1	517	6	0	0
T2	592	2	0	0
T3	491	19	0	0
T4	308	6	0	0
T5	191	1	0	0
T6	2912	54	0	0
T7	3678	102	0	0
T8	13909	278	0	0
T9	10313	190	0	0
T10	33124	382	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	21527	0	0
T1	517	6	0	0
T2	592	2	0	0
T3	491	19	0	0
T4	308	6	0	0
T5	191	1	0	0
T6	2912	54	0	0
T7	3678	102	0	0
T8	13909	278	0	0
T9	10313	190	0	0
T10	33124	382	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	21527	0	0
T1	17279	6	0	0
T2	19741	2	0	0
T3	16458	19	0	0
T4	10286	6	0	0
T5	6386	1	0	0
T6	95399	54	0	0
T7	122082	102	0	0
T8	448815	278	0	0
T9	336976	190	0	0
T10	108699	382	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	21527	0	0
T1	17279	6	0	0
T2	19741	2	0	0
T3	16458	19	0	0
T4	10286	6	0	0
T5	6386	1	0	0
T6	95399	54	0	0
T7	122082	102	0	0
T8	448815	278	0	0
T9	336976	190	0	0
T10	108699	382	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	6797	0	0
T1	517	1	0	0
T2	592	16	0	0
T3	491	1	0	0
T4	308	1	0	0
T5	191	1	0	0
T6	2912	14	0	0
T7	3678	27	0	0
T8	13909	46	0	0
T9	10313	36	0	0
T10	33124	71	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	21527	0	0
T1	17279	6	0	0
T2	19741	2	0	0
T3	16458	19	0	0
T4	10286	6	0	0
T5	6386	1	0	0
T6	95399	54	0	0
T7	122082	102	0	0
T8	448815	278	0	0
T9	336976	190	0	0
T10	108699	382	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52249860	21527	0	0
T1	17279	6	0	0
T2	19741	2	0	0
T3	16458	19	0	0
T4	10286	6	0	0
T5	6386	1	0	0
T6	95399	54	0	0
T7	122082	102	0	0
T8	448815	278	0	0
T9	336976	190	0	0
T10	108699	382	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	218	0	0
T8	13909	6	0	0
T9	10313	2	0	0
T10	33124	3	0	0
T11	455	0	0	0
T20	3889	2	0	0
T21	473	0	0	0
T44	266	0	0	0
T45	730	0	0	0
T46	9930	1	0	0
T47	6036	2	0	0
T80	0	11	0	0
T81	0	5	0	0
T82	0	4	0	0
T93	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	8522	0	0
T1	517	2	0	0
T2	592	2	0	0
T3	491	1	0	0
T4	308	2	0	0
T5	191	1	0	0
T6	2912	20	0	0
T7	3678	27	0	0
T8	13909	91	0	0
T9	10313	65	0	0
T10	33124	139	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	21527	0	0
T1	4147	6	0	0
T2	4736	2	0	0
T3	3948	19	0	0
T4	2468	6	0	0
T5	1531	1	0	0
T6	22897	54	0	0
T7	29304	102	0	0
T8	107707	278	0	0
T9	80898	190	0	0
T10	260901	382	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	21527	0	0
T1	4147	6	0	0
T2	4736	2	0	0
T3	3948	19	0	0
T4	2468	6	0	0
T5	1531	1	0	0
T6	22897	54	0	0
T7	29304	102	0	0
T8	107707	278	0	0
T9	80898	190	0	0
T10	260901	382	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11074966	21527	0	0
T1	3855	6	0	0
T2	4622	2	0	0
T3	2730	19	0	0
T4	2376	6	0	0
T5	1489	1	0	0
T6	17802	54	0	0
T7	26265	102	0	0
T8	83995	278	0	0
T9	64519	190	0	0
T10	229072	382	0	0