Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12539684	13867	0	0
gen_assertions[0].RstEnOn_A	12539684	1049	0	0
gen_assertions[0].RstNOff_A	12539684	13867	0	0
gen_assertions[0].RstNOn_A	12539684	1049	0	0
gen_assertions[1].RstEnOff_A	50158224	12566	0	0
gen_assertions[1].RstEnOn_A	50158224	1024	0	0
gen_assertions[1].RstNOff_A	50158224	12566	0	0
gen_assertions[1].RstNOn_A	50158224	1024	0	0
gen_assertions[2].RstEnOff_A	25079962	12626	0	0
gen_assertions[2].RstEnOn_A	25079962	1005	0	0
gen_assertions[2].RstNOff_A	25079962	12626	0	0
gen_assertions[2].RstNOn_A	25079962	1005	0	0
gen_assertions[3].RstEnOff_A	25080026	12646	0	0
gen_assertions[3].RstEnOn_A	25080026	1011	0	0
gen_assertions[3].RstNOff_A	25080026	12646	0	0
gen_assertions[3].RstNOn_A	25080026	1011	0	0
gen_assertions[4].RstEnOff_A	1583700	21260	0	0
gen_assertions[4].RstEnOn_A	1583700	1079	0	0
gen_assertions[4].RstNOff_A	1583700	21260	0	0
gen_assertions[4].RstNOn_A	1583700	1079	0	0
gen_assertions[5].RstEnOff_A	12539684	14119	0	0
gen_assertions[5].RstEnOn_A	12539684	1141	0	0
gen_assertions[5].RstNOff_A	12539684	14119	0	0
gen_assertions[5].RstNOn_A	12539684	1141	0	0
gen_assertions[6].RstEnOff_A	12539684	14157	0	0
gen_assertions[6].RstEnOn_A	12539684	1192	0	0
gen_assertions[6].RstNOff_A	12539684	14157	0	0
gen_assertions[6].RstNOn_A	12539684	1192	0	0
gen_assertions[7].RstEnOff_A	12539684	14184	0	0
gen_assertions[7].RstEnOn_A	12539684	1215	0	0
gen_assertions[7].RstNOff_A	12539684	14184	0	0
gen_assertions[7].RstNOn_A	12539684	1215	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	13867	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	190	0	0
T9	80898	144	0	0
T10	260901	272	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1049	0	0
T3	3948	9	0	0
T4	2468	0	0	0
T5	1531	0	0	0
T6	22897	0	0	0
T7	29304	0	0	0
T8	107707	4	0	0
T9	80898	19	0	0
T10	260901	29	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T33	0	5	0	0
T37	0	1	0	0
T40	0	1	0	0
T46	0	7	0	0
T79	0	3	0	0
T80	0	4	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	13867	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	190	0	0
T9	80898	144	0	0
T10	260901	272	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1049	0	0
T3	3948	9	0	0
T4	2468	0	0	0
T5	1531	0	0	0
T6	22897	0	0	0
T7	29304	0	0	0
T8	107707	4	0	0
T9	80898	19	0	0
T10	260901	29	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T33	0	5	0	0
T37	0	1	0	0
T40	0	1	0	0
T46	0	7	0	0
T79	0	3	0	0
T80	0	4	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50158224	12566	0	0
T1	16585	4	0	0
T2	18951	0	0	0
T3	15798	16	0	0
T4	9875	2	0	0
T5	6130	0	0	0
T6	91618	30	0	0
T7	117215	72	0	0
T8	430825	177	0	0
T9	323525	128	0	0
T10	104347	247	0	0
T20	0	25	0	0
T21	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50158224	1024	0	0
T3	15798	8	0	0
T4	9875	0	0	0
T5	6130	0	0	0
T6	91618	0	0	0
T7	117215	0	0	0
T8	430825	10	0	0
T9	323525	17	0	0
T10	104347	33	0	0
T11	14644	0	0	0
T20	122245	0	0	0
T33	0	4	0	0
T37	0	1	0	0
T46	0	6	0	0
T79	0	1	0	0
T80	0	6	0	0
T81	0	10	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50158224	12566	0	0
T1	16585	4	0	0
T2	18951	0	0	0
T3	15798	16	0	0
T4	9875	2	0	0
T5	6130	0	0	0
T6	91618	30	0	0
T7	117215	72	0	0
T8	430825	177	0	0
T9	323525	128	0	0
T10	104347	247	0	0
T20	0	25	0	0
T21	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50158224	1024	0	0
T3	15798	8	0	0
T4	9875	0	0	0
T5	6130	0	0	0
T6	91618	0	0	0
T7	117215	0	0	0
T8	430825	10	0	0
T9	323525	17	0	0
T10	104347	33	0	0
T11	14644	0	0	0
T20	122245	0	0	0
T33	0	4	0	0
T37	0	1	0	0
T46	0	6	0	0
T79	0	1	0	0
T80	0	6	0	0
T81	0	10	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25079962	12626	0	0
T1	8292	4	0	0
T2	9475	0	0	0
T3	7899	16	0	0
T4	4939	2	0	0
T5	3064	0	0	0
T6	45801	30	0	0
T7	58599	72	0	0
T8	215420	175	0	0
T9	161776	128	0	0
T10	521770	241	0	0
T20	0	25	0	0
T21	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25079962	1005	0	0
T3	7899	1	0	0
T4	4939	0	0	0
T5	3064	0	0	0
T6	45801	0	0	0
T7	58599	0	0	0
T8	215420	6	0	0
T9	161776	17	0	0
T10	521770	28	0	0
T11	7323	0	0	0
T20	61138	0	0	0
T33	0	9	0	0
T46	0	8	0	0
T52	0	1	0	0
T79	0	1	0	0
T80	0	4	0	0
T81	0	10	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25079962	12626	0	0
T1	8292	4	0	0
T2	9475	0	0	0
T3	7899	16	0	0
T4	4939	2	0	0
T5	3064	0	0	0
T6	45801	30	0	0
T7	58599	72	0	0
T8	215420	175	0	0
T9	161776	128	0	0
T10	521770	241	0	0
T20	0	25	0	0
T21	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25079962	1005	0	0
T3	7899	1	0	0
T4	4939	0	0	0
T5	3064	0	0	0
T6	45801	0	0	0
T7	58599	0	0	0
T8	215420	6	0	0
T9	161776	17	0	0
T10	521770	28	0	0
T11	7323	0	0	0
T20	61138	0	0	0
T33	0	9	0	0
T46	0	8	0	0
T52	0	1	0	0
T79	0	1	0	0
T80	0	4	0	0
T81	0	10	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25080026	12646	0	0
T1	8292	4	0	0
T2	9476	0	0	0
T3	7899	16	0	0
T4	4940	2	0	0
T5	3064	0	0	0
T6	45795	30	0	0
T7	58626	72	0	0
T8	215424	175	0	0
T9	161778	132	0	0
T10	521781	242	0	0
T20	0	25	0	0
T21	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25080026	1011	0	0
T8	215424	7	0	0
T9	161778	21	0	0
T10	521781	28	0	0
T11	7322	0	0	0
T20	61134	0	0	0
T21	7597	0	0	0
T33	0	8	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	4262	0	0	0
T45	11650	0	0	0
T46	157523	8	0	0
T47	96104	0	0	0
T80	0	5	0	0
T81	0	13	0	0
T82	0	19	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25080026	12646	0	0
T1	8292	4	0	0
T2	9476	0	0	0
T3	7899	16	0	0
T4	4940	2	0	0
T5	3064	0	0	0
T6	45795	30	0	0
T7	58626	72	0	0
T8	215424	175	0	0
T9	161778	132	0	0
T10	521781	242	0	0
T20	0	25	0	0
T21	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25080026	1011	0	0
T8	215424	7	0	0
T9	161778	21	0	0
T10	521781	28	0	0
T11	7322	0	0	0
T20	61134	0	0	0
T21	7597	0	0	0
T33	0	8	0	0
T37	0	1	0	0
T40	0	1	0	0
T44	4262	0	0	0
T45	11650	0	0	0
T46	157523	8	0	0
T47	96104	0	0	0
T80	0	5	0	0
T81	0	13	0	0
T82	0	19	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	21260	0	0
T1	517	6	0	0
T2	592	2	0	0
T3	491	19	0	0
T4	308	5	0	0
T5	191	1	0	0
T6	2912	53	0	0
T7	3678	75	0	0
T8	13909	280	0	0
T9	10313	206	0	0
T10	33124	407	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	1079	0	0
T8	13909	8	0	0
T9	10313	18	0	0
T10	33124	29	0	0
T11	455	0	0	0
T20	3889	0	0	0
T21	473	0	0	0
T33	0	8	0	0
T44	266	0	0	0
T45	730	0	0	0
T46	9930	8	0	0
T47	6036	0	0	0
T80	0	6	0	0
T81	0	12	0	0
T82	0	24	0	0
T83	0	1	0	0
T84	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	21260	0	0
T1	517	6	0	0
T2	592	2	0	0
T3	491	19	0	0
T4	308	5	0	0
T5	191	1	0	0
T6	2912	53	0	0
T7	3678	75	0	0
T8	13909	280	0	0
T9	10313	206	0	0
T10	33124	407	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1583700	1079	0	0
T8	13909	8	0	0
T9	10313	18	0	0
T10	33124	29	0	0
T11	455	0	0	0
T20	3889	0	0	0
T21	473	0	0	0
T33	0	8	0	0
T44	266	0	0	0
T45	730	0	0	0
T46	9930	8	0	0
T47	6036	0	0	0
T80	0	6	0	0
T81	0	12	0	0
T82	0	24	0	0
T83	0	1	0	0
T84	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	14119	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	191	0	0
T9	80898	141	0	0
T10	260901	275	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1141	0	0
T8	107707	4	0	0
T9	80898	17	0	0
T10	260901	32	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T21	3797	0	0	0
T33	0	9	0	0
T44	2131	0	0	0
T45	5824	0	0	0
T46	78762	6	0	0
T47	48050	0	0	0
T58	0	1	0	0
T80	0	5	0	0
T81	0	11	0	0
T82	0	22	0	0
T85	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	14119	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	191	0	0
T9	80898	141	0	0
T10	260901	275	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1141	0	0
T8	107707	4	0	0
T9	80898	17	0	0
T10	260901	32	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T21	3797	0	0	0
T33	0	9	0	0
T44	2131	0	0	0
T45	5824	0	0	0
T46	78762	6	0	0
T47	48050	0	0	0
T58	0	1	0	0
T80	0	5	0	0
T81	0	11	0	0
T82	0	22	0	0
T85	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	14157	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	193	0	0
T9	80898	144	0	0
T10	260901	272	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1192	0	0
T8	107707	6	0	0
T9	80898	19	0	0
T10	260901	30	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T21	3797	0	0	0
T33	0	10	0	0
T44	2131	0	0	0
T45	5824	0	0	0
T46	78762	9	0	0
T47	48050	0	0	0
T58	0	1	0	0
T80	0	6	0	0
T81	0	10	0	0
T82	0	23	0	0
T86	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	14157	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	193	0	0
T9	80898	144	0	0
T10	260901	272	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1192	0	0
T8	107707	6	0	0
T9	80898	19	0	0
T10	260901	30	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T21	3797	0	0	0
T33	0	10	0	0
T44	2131	0	0	0
T45	5824	0	0	0
T46	78762	9	0	0
T47	48050	0	0	0
T58	0	1	0	0
T80	0	6	0	0
T81	0	10	0	0
T82	0	23	0	0
T86	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	14184	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	191	0	0
T9	80898	140	0	0
T10	260901	273	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1215	0	0
T8	107707	5	0	0
T9	80898	16	0	0
T10	260901	30	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T21	3797	0	0	0
T33	0	12	0	0
T44	2131	0	0	0
T45	5824	0	0	0
T46	78762	4	0	0
T47	48050	0	0	0
T53	0	16	0	0
T80	0	5	0	0
T81	0	12	0	0
T82	0	22	0	0
T86	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	14184	0	0
T1	4147	4	0	0
T2	4736	0	0	0
T3	3948	18	0	0
T4	2468	4	0	0
T5	1531	0	0	0
T6	22897	34	0	0
T7	29304	75	0	0
T8	107707	191	0	0
T9	80898	140	0	0
T10	260901	273	0	0
T20	0	29	0	0
T21	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539684	1215	0	0
T8	107707	5	0	0
T9	80898	16	0	0
T10	260901	30	0	0
T11	3660	0	0	0
T20	30570	0	0	0
T21	3797	0	0	0
T33	0	12	0	0
T44	2131	0	0	0
T45	5824	0	0	0
T46	78762	4	0	0
T47	48050	0	0	0
T53	0	16	0	0
T80	0	5	0	0
T81	0	12	0	0
T82	0	22	0	0
T86	0	1	0	0