Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11846874	9248	0	0
alert_regwen_rd_A	11846874	4620	0	0
cpu_regwen_rd_A	11846874	4918	0	0
sw_rst_ctrl_n_0_rd_A	11846874	8849	0	0
sw_rst_ctrl_n_1_rd_A	11846874	8821	0	0
sw_rst_ctrl_n_2_rd_A	11846874	8704	0	0
sw_rst_ctrl_n_3_rd_A	11846874	8853	0	0
sw_rst_ctrl_n_4_rd_A	11846874	8836	0	0
sw_rst_ctrl_n_5_rd_A	11846874	8950	0	0
sw_rst_ctrl_n_6_rd_A	11846874	9143	0	0
sw_rst_ctrl_n_7_rd_A	11846874	9050	0	0
sw_rst_regwen_0_rd_A	11846874	5135	0	0
sw_rst_regwen_1_rd_A	11846874	5107	0	0
sw_rst_regwen_2_rd_A	11846874	5079	0	0
sw_rst_regwen_3_rd_A	11846874	5226	0	0
sw_rst_regwen_4_rd_A	11846874	5013	0	0
sw_rst_regwen_5_rd_A	11846874	5132	0	0
sw_rst_regwen_6_rd_A	11846874	5211	0	0
sw_rst_regwen_7_rd_A	11846874	4971	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	9248	0	0
T56	18843	4	0	0
T60	11801	647	0	0
T61	9298	541	0	0
T62	10055	573	0	0
T66	20504	3	0	0
T67	2400	7	0	0
T87	9329	330	0	0
T88	4345	17	0	0
T89	8944	273	0	0
T90	17375	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	4620	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	0	0	0
T47	42373	89	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	75	0	0
T95	0	199	0	0
T114	0	63	0	0
T115	0	31	0	0
T116	0	297	0	0
T117	0	78	0	0
T118	0	194	0	0
T119	0	390	0	0
T120	0	26	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	4918	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	0	0	0
T47	42373	98	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	102	0	0
T95	0	273	0	0
T114	0	74	0	0
T115	0	38	0	0
T116	0	310	0	0
T117	0	88	0	0
T118	0	162	0	0
T119	0	388	0	0
T120	0	56	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	8849	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	9	0	0
T47	42373	89	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	79	0	0
T114	0	55	0	0
T115	0	117	0	0
T121	0	13	0	0
T122	0	25	0	0
T123	0	16	0	0
T124	0	13	0	0
T125	0	95	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	8821	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	12	0	0
T47	42373	42	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	63	0	0
T114	0	72	0	0
T115	0	129	0	0
T121	0	7	0	0
T122	0	30	0	0
T123	0	17	0	0
T124	0	25	0	0
T125	0	76	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	8704	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	15	0	0
T47	42373	98	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	57	0	0
T114	0	75	0	0
T115	0	133	0	0
T121	0	10	0	0
T122	0	44	0	0
T123	0	27	0	0
T124	0	14	0	0
T125	0	47	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	8853	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	16	0	0
T47	42373	84	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	57	0	0
T114	0	73	0	0
T115	0	115	0	0
T121	0	16	0	0
T122	0	29	0	0
T123	0	22	0	0
T124	0	14	0	0
T125	0	85	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	8836	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	17	0	0
T47	42373	76	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	83	0	0
T114	0	56	0	0
T115	0	141	0	0
T121	0	14	0	0
T122	0	43	0	0
T123	0	15	0	0
T124	0	8	0	0
T125	0	94	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	8950	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	8	0	0
T47	42373	89	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	84	0	0
T114	0	68	0	0
T115	0	116	0	0
T121	0	11	0	0
T122	0	19	0	0
T123	0	7	0	0
T124	0	16	0	0
T125	0	96	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	9143	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	12	0	0
T47	42373	96	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	92	0	0
T114	0	62	0	0
T115	0	112	0	0
T121	0	7	0	0
T122	0	32	0	0
T123	0	8	0	0
T124	0	16	0	0
T125	0	73	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	9050	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	9	0	0
T47	42373	73	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	96	0	0
T114	0	86	0	0
T115	0	126	0	0
T121	0	10	0	0
T122	0	40	0	0
T123	0	5	0	0
T124	0	14	0	0
T125	0	106	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	5135	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	0	0	0
T47	42373	77	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	62	0	0
T95	0	205	0	0
T114	0	50	0	0
T115	0	90	0	0
T116	0	250	0	0
T117	0	65	0	0
T125	0	17	0	0
T126	0	9	0	0
T127	0	12	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	5107	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	9	0	0
T47	42373	97	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	77	0	0
T95	0	234	0	0
T114	0	55	0	0
T115	0	57	0	0
T116	0	292	0	0
T125	0	24	0	0
T126	0	4	0	0
T127	0	8	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	5079	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	7	0	0
T47	42373	86	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	73	0	0
T95	0	183	0	0
T114	0	54	0	0
T115	0	60	0	0
T116	0	232	0	0
T125	0	17	0	0
T126	0	8	0	0
T127	0	6	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	5226	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	2	0	0
T47	42373	92	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	92	0	0
T95	0	221	0	0
T114	0	54	0	0
T115	0	70	0	0
T116	0	284	0	0
T125	0	10	0	0
T126	0	1	0	0
T127	0	8	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	5013	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	11	0	0
T47	42373	90	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	86	0	0
T95	0	224	0	0
T114	0	82	0	0
T115	0	59	0	0
T116	0	298	0	0
T125	0	12	0	0
T126	0	5	0	0
T127	0	10	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	5132	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	8	0	0
T47	42373	74	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	81	0	0
T95	0	239	0	0
T114	0	65	0	0
T115	0	72	0	0
T116	0	299	0	0
T125	0	10	0	0
T126	0	6	0	0
T127	0	10	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	5211	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	1	0	0
T47	42373	78	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	80	0	0
T95	0	217	0	0
T114	0	58	0	0
T115	0	52	0	0
T116	0	305	0	0
T125	0	24	0	0
T126	0	6	0	0
T127	0	5	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11846874	4971	0	0
T22	41985	0	0	0
T32	1453	0	0	0
T33	3459	0	0	0
T34	26227	0	0	0
T35	5287	0	0	0
T36	5281	0	0	0
T37	5554	3	0	0
T47	42373	90	0	0
T52	4458	0	0	0
T79	1892	0	0	0
T94	0	76	0	0
T95	0	222	0	0
T114	0	48	0	0
T115	0	69	0	0
T116	0	272	0	0
T125	0	17	0	0
T126	0	4	0	0
T127	0	5	0	0