Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sw_rst_ctrl_n[0]	100.00	1	100	1	64	64
sw_rst_ctrl_n[1]	100.00	1	100	1	64	64
sw_rst_ctrl_n[2]	100.00	1	100	1	64	64
sw_rst_ctrl_n[3]	100.00	1	100	1	64	64
sw_rst_ctrl_n[4]	100.00	1	100	1	64	64
sw_rst_ctrl_n[5]	100.00	1	100	1	64	64
sw_rst_ctrl_n[6]	100.00	1	100	1	64	64
sw_rst_ctrl_n[7]	100.00	1	100	1	64	64

---

Group Instance : sw_rst_ctrl_n[0]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[0]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[0]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[1]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[1]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[1]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[2]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[2]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[2]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[3]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[3]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[3]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[4]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[4]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[4]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[5]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[5]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[5]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[6]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[6]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[6]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[7]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[7]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[7]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T10

32

T39

32

T49

32

auto[1]

4931

1

T4

3

T10

31

T11

10

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T10

32

T39

32

T49

32

auto[1]

4931

1

T4

3

T10

31

T11

10

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1870

1

T10

19

T11

4

T19

28

auto[1]

4661

1

T4

3

T10

44

T11

6

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1870

1

T10

19

T11

4

T19

28

auto[1]

4661

1

T4

3

T10

44

T11

6

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

400

1

T10

8

T39

8

T49

8

auto[0]

auto[1]

1200

1

T10

24

T39

24

T49

24

auto[1]

auto[0]

1470

1

T10

11

T11

4

T19

28

auto[1]

auto[1]

3461

1

T4

3

T10

20

T11

6

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1472

1

T10

28

T39

28

T53

3

auto[1]

4809

1

T4

3

T10

35

T11

9

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1472

1

T10

28

T39

28

T53

3

auto[1]

4809

1

T4

3

T10

35

T11

9

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794

1

T10

15

T11

2

T19

35

auto[1]

4487

1

T4

3

T10

48

T11

7

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794

1

T10

15

T11

2

T19

35

auto[1]

4487

1

T4

3

T10

48

T11

7

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

383

1

T10

7

T39

7

T53

1

auto[0]

auto[1]

1089

1

T10

21

T39

21

T53

2

auto[1]

auto[0]

1411

1

T10

8

T11

2

T19

35

auto[1]

auto[1]

3398

1

T4

3

T10

27

T11

7

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1269

1

T10

24

T38

3

T39

24

auto[1]

4841

1

T4

3

T10

39

T11

6

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1269

1

T10

24

T38

3

T39

24

auto[1]

4841

1

T4

3

T10

39

T11

6

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1725

1

T4

1

T10

19

T19

38

auto[1]

4385

1

T4

2

T10

44

T11

6

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1725

1

T4

1

T10

19

T19

38

auto[1]

4385

1

T4

2

T10

44

T11

6

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

332

1

T10

6

T38

1

T39

6

auto[0]

auto[1]

937

1

T10

18

T38

2

T39

18

auto[1]

auto[0]

1393

1

T4

1

T10

13

T19

38

auto[1]

auto[1]

3448

1

T4

2

T10

26

T11

6

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T10

20

T39

20

T49

20

auto[1]

5009

1

T4

3

T10

43

T11

5

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T10

20

T39

20

T49

20

auto[1]

5009

1

T4

3

T10

43

T11

5

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1717

1

T10

17

T19

23

T38

1

auto[1]

4367

1

T4

3

T10

46

T11

5

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1717

1

T10

17

T19

23

T38

1

auto[1]

4367

1

T4

3

T10

46

T11

5

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

289

1

T10

5

T39

5

T49

5

auto[0]

auto[1]

786

1

T10

15

T39

15

T49

15

auto[1]

auto[0]

1428

1

T10

12

T19

23

T38

1

auto[1]

auto[1]

3581

1

T4

3

T10

31

T11

5

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

878

1

T4

3

T10

16

T38

3

auto[1]

5206

1

T10

47

T11

5

T19

93

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

878

1

T4

3

T10

16

T38

3

auto[1]

5206

1

T10

47

T11

5

T19

93

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1695

1

T4

1

T10

17

T19

27

auto[1]

4389

1

T4

2

T10

46

T11

5

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1695

1

T4

1

T10

17

T19

27

auto[1]

4389

1

T4

2

T10

46

T11

5

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

237

1

T4

1

T10

4

T38

1

auto[0]

auto[1]

641

1

T4

2

T10

12

T38

2

auto[1]

auto[0]

1458

1

T10

13

T19

27

T39

12

auto[1]

auto[1]

3748

1

T10

34

T11

5

T19

66

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T4

3

T10

12

T38

3

auto[1]

5397

1

T10

51

T11

5

T19

93

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T4

3

T10

12

T38

3

auto[1]

5397

1

T10

51

T11

5

T19

93

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T4

1

T10

21

T19

32

auto[1]

4374

1

T4

2

T10

42

T11

5

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1710

1

T4

1

T10

21

T19

32

auto[1]

4374

1

T4

2

T10

42

T11

5

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

193

1

T4

1

T10

3

T38

2

auto[0]

auto[1]

494

1

T4

2

T10

9

T38

1

auto[1]

auto[0]

1517

1

T10

18

T19

32

T39

13

auto[1]

auto[1]

3880

1

T10

33

T11

5

T19

61

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

466

1

T4

3

T10

8

T38

3

auto[1]

5618

1

T10

55

T11

5

T19

93

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

466

1

T4

3

T10

8

T38

3

auto[1]

5618

1

T10

55

T11

5

T19

93

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1709

1

T4

1

T10

21

T19

31

auto[1]

4375

1

T4

2

T10

42

T11

5

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1709

1

T4

1

T10

21

T19

31

auto[1]

4375

1

T4

2

T10

42

T11

5

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

130

1

T4

1

T10

2

T38

2

auto[0]

auto[1]

336

1

T4

2

T10

6

T38

1

auto[1]

auto[0]

1579

1

T10

19

T19

31

T39

13

auto[1]

auto[1]

4039

1

T10

36

T11

5

T19

62

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

260

1

T10

4

T38

3

T39

4

auto[1]

5824

1

T4

3

T10

59

T11

5

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

260

1

T10

4

T38

3

T39

4

auto[1]

5824

1

T4

3

T10

59

T11

5

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1696

1

T10

21

T19

23

T38

1

auto[1]

4388

1

T4

3

T10

42

T11

5

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1696

1

T10

21

T19

23

T38

1

auto[1]

4388

1

T4

3

T10

42

T11

5

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

80

1

T10

1

T38

1

T39

1

auto[0]

auto[1]

180

1

T10

3

T38

2

T39

3

auto[1]

auto[0]

1616

1

T10

20

T19

23

T39

14

auto[1]

auto[1]

4208

1

T4

3

T10

39

T11

5