Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	632195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

381692

1

T1

68

T4

139

T5

1049

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	541203	1			T1	99		T2	1		T3	1
values[0x0]	235797	1			T1	61		T4	101		T5	840
values[0x1]	236887	1			T1	52		T4	92		T5	860

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	531620	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

482267

1

T1

84

T4

179

T5

1391

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3447	1			T1	1		T4	5		T5	8
valid_sources[0x01]	5001	1			T1	2		T4	1		T5	3
valid_sources[0x02]	4420	1			T1	1		T4	5		T5	2
valid_sources[0x03]	3334	1			T4	2		T5	1		T6	12
valid_sources[0x04]	6838	1			T4	1		T5	10		T6	11
valid_sources[0x05]	3206	1			T4	3		T5	12		T6	8
valid_sources[0x06]	3508	1			T4	2		T5	15		T6	13
valid_sources[0x07]	5334	1			T1	1		T5	13		T6	7
valid_sources[0x08]	3249	1			T4	3		T5	22		T6	10
valid_sources[0x09]	6801	1			T1	2		T4	1		T5	5
valid_sources[0x0a]	3053	1			T1	1		T5	21		T6	4
valid_sources[0x0b]	3981	1			T1	4		T5	16		T6	11
valid_sources[0x0c]	4355	1			T1	1		T5	7		T6	8
valid_sources[0x0d]	4412	1			T1	1		T5	27		T6	9
valid_sources[0x0e]	3823	1			T5	8		T6	14		T9	2
valid_sources[0x0f]	4647	1			T1	1		T5	23		T6	6
valid_sources[0x10]	3631	1			T5	36		T6	9		T24	5
valid_sources[0x11]	3125	1			T1	1		T5	5		T6	9
valid_sources[0x12]	3658	1			T1	1		T4	1		T5	8
valid_sources[0x13]	3491	1			T1	2		T5	18		T6	7
valid_sources[0x14]	3799	1			T4	2		T5	1		T6	8
valid_sources[0x15]	4651	1			T5	21		T6	20		T64	1
valid_sources[0x16]	4314	1			T4	4		T6	6		T21	1
valid_sources[0x17]	3232	1			T1	1		T4	2		T5	6
valid_sources[0x18]	3209	1			T1	2		T4	2		T6	14
valid_sources[0x19]	3683	1			T1	2		T4	4		T5	2
valid_sources[0x1a]	3828	1			T1	3		T4	4		T5	5
valid_sources[0x1b]	3970	1			T1	1		T4	1		T6	9
valid_sources[0x1c]	3935	1			T1	2		T5	40		T6	10
valid_sources[0x1d]	3989	1			T5	7		T6	9		T9	1
valid_sources[0x1e]	3515	1			T1	1		T6	2		T9	1
valid_sources[0x1f]	3427	1			T4	1		T5	15		T6	11
valid_sources[0x20]	5529	1			T1	1		T4	3		T5	11
valid_sources[0x21]	4513	1			T2	1		T5	29		T6	10
valid_sources[0x22]	3149	1			T1	1		T5	11		T6	3
valid_sources[0x23]	3299	1			T5	6		T6	13		T9	2
valid_sources[0x24]	3458	1			T1	2		T4	1		T6	8
valid_sources[0x25]	3330	1			T4	7		T5	10		T6	9
valid_sources[0x26]	3347	1			T1	1		T4	1		T5	16
valid_sources[0x27]	6839	1			T1	1		T4	2		T5	13
valid_sources[0x28]	3214	1			T1	2		T4	3		T5	4
valid_sources[0x29]	7105	1			T4	3		T5	7		T6	8
valid_sources[0x2a]	4286	1			T1	1		T4	6		T5	20
valid_sources[0x2b]	3315	1			T5	16		T6	10		T9	2
valid_sources[0x2c]	3399	1			T4	1		T5	10		T6	9
valid_sources[0x2d]	3530	1			T4	1		T5	35		T6	12
valid_sources[0x2e]	3971	1			T4	1		T5	5		T6	9
valid_sources[0x2f]	3434	1			T1	1		T4	1		T5	21
valid_sources[0x30]	3364	1			T1	1		T5	2		T6	8
valid_sources[0x31]	4087	1			T1	1		T4	7		T5	33
valid_sources[0x32]	5325	1			T1	2		T4	2		T5	7
valid_sources[0x33]	3331	1			T1	2		T4	1		T5	10
valid_sources[0x34]	3465	1			T5	32		T6	6		T9	2
valid_sources[0x35]	4291	1			T5	11		T6	7		T9	1
valid_sources[0x36]	2933	1			T1	2		T4	1		T5	5
valid_sources[0x37]	3813	1			T4	1		T5	36		T6	14
valid_sources[0x38]	3541	1			T4	3		T5	10		T6	5
valid_sources[0x39]	3241	1			T1	1		T5	14		T6	10
valid_sources[0x3a]	3310	1			T1	1		T4	1		T5	31
valid_sources[0x3b]	3580	1			T4	4		T5	7		T6	8
valid_sources[0x3c]	4016	1			T1	2		T4	2		T5	21
valid_sources[0x3d]	6331	1			T1	3		T5	10		T6	7
valid_sources[0x3e]	4717	1			T1	1		T4	1		T5	7
valid_sources[0x3f]	3284	1			T4	1		T5	25		T6	8
valid_sources[0x40]	5457	1			T4	4		T5	3		T6	16
valid_sources[0x41]	5907	1			T1	1		T4	2		T5	1
valid_sources[0x42]	4798	1			T1	1		T5	19		T6	8
valid_sources[0x43]	3575	1			T4	3		T5	4		T6	13
valid_sources[0x44]	4010	1			T5	6		T6	9		T9	2
valid_sources[0x45]	3928	1			T4	1		T5	2		T6	13
valid_sources[0x46]	3820	1			T4	6		T5	6		T6	12
valid_sources[0x47]	3290	1			T1	2		T4	1		T5	44
valid_sources[0x48]	3197	1			T4	1		T5	23		T6	8
valid_sources[0x49]	3632	1			T1	1		T5	17		T6	9
valid_sources[0x4a]	3549	1			T4	3		T5	3		T6	7
valid_sources[0x4b]	3585	1			T4	1		T5	20		T6	8
valid_sources[0x4c]	3407	1			T5	15		T6	13		T9	1
valid_sources[0x4d]	3495	1			T1	1		T5	7		T6	7
valid_sources[0x4e]	3470	1			T1	2		T4	1		T5	12
valid_sources[0x4f]	3593	1			T1	1		T4	3		T5	1
valid_sources[0x50]	4903	1			T5	21		T6	7		T9	2
valid_sources[0x51]	3478	1			T5	9		T6	11		T9	3
valid_sources[0x52]	4569	1			T1	2		T5	27		T6	8
valid_sources[0x53]	3471	1			T1	3		T5	22		T6	4
valid_sources[0x54]	3121	1			T5	6		T6	8		T9	1
valid_sources[0x55]	3562	1			T1	1		T4	3		T5	6
valid_sources[0x56]	3486	1			T5	4		T6	15		T9	1
valid_sources[0x57]	3712	1			T1	1		T4	6		T5	51
valid_sources[0x58]	4167	1			T1	1		T5	25		T6	7
valid_sources[0x59]	3151	1			T1	1		T4	1		T5	5
valid_sources[0x5a]	4054	1			T4	1		T5	25		T6	12
valid_sources[0x5b]	3449	1			T1	3		T4	1		T5	4
valid_sources[0x5c]	4291	1			T1	1		T5	24		T6	11
valid_sources[0x5d]	3827	1			T1	1		T4	1		T5	5
valid_sources[0x5e]	3398	1			T4	2		T5	3		T6	5
valid_sources[0x5f]	3733	1			T1	1		T5	12		T6	4
valid_sources[0x60]	4046	1			T4	2		T5	6		T6	8
valid_sources[0x61]	4467	1			T1	2		T5	10		T6	9
valid_sources[0x62]	3887	1			T1	2		T5	7		T6	4
valid_sources[0x63]	5440	1			T4	1		T5	10		T6	6
valid_sources[0x64]	6817	1			T1	2		T5	16		T6	8
valid_sources[0x65]	4319	1			T1	2		T4	2		T6	11
valid_sources[0x66]	3291	1			T5	8		T6	7		T24	11
valid_sources[0x67]	4118	1			T1	1		T5	6		T6	9
valid_sources[0x68]	4144	1			T5	3		T6	11		T24	8
valid_sources[0x69]	4996	1			T4	1		T5	13		T6	14
valid_sources[0x6a]	3609	1			T1	2		T4	1		T5	2
valid_sources[0x6b]	3467	1			T1	1		T4	2		T6	11
valid_sources[0x6c]	3991	1			T4	2		T5	3		T6	9
valid_sources[0x6d]	4239	1			T4	1		T5	5		T6	7
valid_sources[0x6e]	3439	1			T5	22		T6	10		T9	1
valid_sources[0x6f]	7286	1			T1	1		T4	2		T5	15
valid_sources[0x70]	3502	1			T1	2		T5	12		T6	12
valid_sources[0x71]	4077	1			T4	2		T6	14		T64	1
valid_sources[0x72]	3849	1			T4	2		T5	18		T6	6
valid_sources[0x73]	3466	1			T4	5		T5	10		T6	12
valid_sources[0x74]	4407	1			T1	2		T4	1		T5	5
valid_sources[0x75]	3312	1			T5	30		T6	10		T9	2
valid_sources[0x76]	3517	1			T4	1		T5	35		T6	9
valid_sources[0x77]	3682	1			T1	3		T4	3		T5	11
valid_sources[0x78]	3006	1			T4	2		T5	18		T6	6
valid_sources[0x79]	5119	1			T5	15		T6	8		T9	2
valid_sources[0x7a]	2895	1			T1	1		T4	5		T5	17
valid_sources[0x7b]	3530	1			T4	1		T5	10		T6	17
valid_sources[0x7c]	3920	1			T1	1		T4	2		T5	15
valid_sources[0x7d]	3297	1			T1	1		T4	1		T5	32
valid_sources[0x7e]	3882	1			T4	2		T5	12		T6	8
valid_sources[0x7f]	3763	1			T1	1		T4	3		T5	19
valid_sources[0x80]	8303	1			T5	22		T6	6		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

254276

1

T1

42

T4

92

T5

643

values[0x0]

all_enables

biggest_size

82625

1

T1

20

T4

32

T5

268

values[0x1]

all_enables

biggest_size

44791

1

T1

6

T4

15

T5

138