Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12113777	13516	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12113777	124662	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12113777	7038980	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12113777	199068	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12113777	13516	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12113777	124662	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12113777	7038980	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12113777	199068	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	13516	0	0
T1	2488	4	0	0
T2	3998	0	0	0
T3	3556	0	0	0
T4	2759	4	0	0
T5	48532	75	0	0
T6	32679	29	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	4	0	0
T10	13173	0	0	0
T11	0	5	0	0
T19	0	164	0	0
T20	0	17	0	0
T21	0	2	0	0
T22	0	5	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	124662	0	0
T1	2488	37	0	0
T2	3998	0	0	0
T3	3556	0	0	0
T4	2759	38	0	0
T5	48532	701	0	0
T6	32679	265	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	38	0	0
T10	13173	0	0	0
T11	0	45	0	0
T19	0	1490	0	0
T20	0	153	0	0
T21	0	18	0	0
T22	0	45	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	7038980	0	0
T1	2488	1469	0	0
T2	3998	922	0	0
T3	3556	835	0	0
T4	2759	1734	0	0
T5	48532	31521	0	0
T6	32679	25054	0	0
T7	1643	995	0	0
T8	2247	716	0	0
T9	3539	2527	0	0
T10	13173	12574	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	199068	0	0
T1	2488	64	0	0
T2	3998	0	0	0
T3	3556	0	0	0
T4	2759	68	0	0
T5	48532	1051	0	0
T6	32679	440	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	62	0	0
T10	13173	0	0	0
T11	0	73	0	0
T19	0	2435	0	0
T20	0	256	0	0
T21	0	36	0	0
T22	0	68	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	13516	0	0
T1	2488	4	0	0
T2	3998	0	0	0
T3	3556	0	0	0
T4	2759	4	0	0
T5	48532	75	0	0
T6	32679	29	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	4	0	0
T10	13173	0	0	0
T11	0	5	0	0
T19	0	164	0	0
T20	0	17	0	0
T21	0	2	0	0
T22	0	5	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	124662	0	0
T1	2488	37	0	0
T2	3998	0	0	0
T3	3556	0	0	0
T4	2759	38	0	0
T5	48532	701	0	0
T6	32679	265	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	38	0	0
T10	13173	0	0	0
T11	0	45	0	0
T19	0	1490	0	0
T20	0	153	0	0
T21	0	18	0	0
T22	0	45	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	7038980	0	0
T1	2488	1469	0	0
T2	3998	922	0	0
T3	3556	835	0	0
T4	2759	1734	0	0
T5	48532	31521	0	0
T6	32679	25054	0	0
T7	1643	995	0	0
T8	2247	716	0	0
T9	3539	2527	0	0
T10	13173	12574	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	199068	0	0
T1	2488	64	0	0
T2	3998	0	0	0
T3	3556	0	0	0
T4	2759	68	0	0
T5	48532	1051	0	0
T6	32679	440	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	62	0	0
T10	13173	0	0	0
T11	0	73	0	0
T19	0	2435	0	0
T20	0	256	0	0
T21	0	36	0	0
T22	0	68	0	0