Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T6,T19,T64
1	0	Covered	T6,T19,T38

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56860090	9325	0	0
CascadeEffAonToRstPorAboveRise_A	56860090	9325	0	0
CascadeEffAonToRstPorIoAboveFall_A	54583979	9325	0	0
CascadeEffAonToRstPorIoAboveRise_A	54583979	9325	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27292865	9325	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27292865	9325	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13645948	9325	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13645948	9325	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27293044	9325	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27293044	9325	0	0
CascadeLcToLcAboveFall_A	56860090	22841	0	0
CascadeLcToLcAboveRise_A	56860090	22841	0	0
CascadeLcToLcAonAboveFall_A	1723402	22841	0	0
CascadeLcToLcAonAboveRise_A	1723402	22841	0	0
CascadeLcToLcShadowedAboveFall_A	56860090	22841	0	0
CascadeLcToLcShadowedAboveRise_A	56860090	22841	0	0
CascadePorToAonAboveFall_A	1723402	7413	0	0
CascadeSysToSysAboveFall_A	56860090	22841	0	0
CascadeSysToSysAboveRise_A	56860090	22841	0	0
ScanRstToAonRise_A	1723402	258	0	0
StablePorToAonRise_A	1723402	9325	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12113777	22841	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12113777	22841	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12113777	22841	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12113777	22841	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13645948	22841	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13645948	22841	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12113777	22841	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12113777	22841	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12113777	22841	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12113777	22841	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	9325	0	0
T1	10974	2	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	2	0	0
T5	216800	27	0	0
T6	151210	16	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	2	0	0
T10	55167	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	9325	0	0
T1	10974	2	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	2	0	0
T5	216800	27	0	0
T6	151210	16	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	2	0	0
T10	55167	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54583979	9325	0	0
T1	10538	2	0	0
T2	16452	2	0	0
T3	14782	2	0	0
T4	11622	2	0	0
T5	208109	27	0	0
T6	145140	16	0	0
T7	6648	1	0	0
T8	9357	2	0	0
T9	14936	2	0	0
T10	52959	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54583979	9325	0	0
T1	10538	2	0	0
T2	16452	2	0	0
T3	14782	2	0	0
T4	11622	2	0	0
T5	208109	27	0	0
T6	145140	16	0	0
T7	6648	1	0	0
T8	9357	2	0	0
T9	14936	2	0	0
T10	52959	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27292865	9325	0	0
T1	5270	2	0	0
T2	8225	2	0	0
T3	7391	2	0	0
T4	5813	2	0	0
T5	104060	27	0	0
T6	72567	16	0	0
T7	3323	1	0	0
T8	4679	2	0	0
T9	7466	2	0	0
T10	26480	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27292865	9325	0	0
T1	5270	2	0	0
T2	8225	2	0	0
T3	7391	2	0	0
T4	5813	2	0	0
T5	104060	27	0	0
T6	72567	16	0	0
T7	3323	1	0	0
T8	4679	2	0	0
T9	7466	2	0	0
T10	26480	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	9325	0	0
T1	2634	2	0	0
T2	4112	2	0	0
T3	3694	2	0	0
T4	2906	2	0	0
T5	52029	27	0	0
T6	36288	16	0	0
T7	1660	1	0	0
T8	2338	2	0	0
T9	3731	2	0	0
T10	13238	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	9325	0	0
T1	2634	2	0	0
T2	4112	2	0	0
T3	3694	2	0	0
T4	2906	2	0	0
T5	52029	27	0	0
T6	36288	16	0	0
T7	1660	1	0	0
T8	2338	2	0	0
T9	3731	2	0	0
T10	13238	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27293044	9325	0	0
T1	5267	2	0	0
T2	8226	2	0	0
T3	7391	2	0	0
T4	5813	2	0	0
T5	104060	27	0	0
T6	72573	16	0	0
T7	3324	1	0	0
T8	4678	2	0	0
T9	7465	2	0	0
T10	26480	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27293044	9325	0	0
T1	5267	2	0	0
T2	8226	2	0	0
T3	7391	2	0	0
T4	5813	2	0	0
T5	104060	27	0	0
T6	72573	16	0	0
T7	3324	1	0	0
T8	4678	2	0	0
T9	7465	2	0	0
T10	26480	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	22841	0	0
T1	10974	6	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	6	0	0
T5	216800	102	0	0
T6	151210	45	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	6	0	0
T10	55167	1	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	22841	0	0
T1	10974	6	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	6	0	0
T5	216800	102	0	0
T6	151210	45	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	6	0	0
T10	55167	1	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	22841	0	0
T1	327	6	0	0
T2	512	2	0	0
T3	460	2	0	0
T4	361	6	0	0
T5	6518	102	0	0
T6	4585	45	0	0
T7	206	1	0	0
T8	290	2	0	0
T9	465	6	0	0
T10	1653	1	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	22841	0	0
T1	327	6	0	0
T2	512	2	0	0
T3	460	2	0	0
T4	361	6	0	0
T5	6518	102	0	0
T6	4585	45	0	0
T7	206	1	0	0
T8	290	2	0	0
T9	465	6	0	0
T10	1653	1	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	22841	0	0
T1	10974	6	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	6	0	0
T5	216800	102	0	0
T6	151210	45	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	6	0	0
T10	55167	1	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	22841	0	0
T1	10974	6	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	6	0	0
T5	216800	102	0	0
T6	151210	45	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	6	0	0
T10	55167	1	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	7413	0	0
T1	327	1	0	0
T2	512	14	0	0
T3	460	10	0	0
T4	361	1	0	0
T5	6518	27	0	0
T6	4585	9	0	0
T7	206	1	0	0
T8	290	5	0	0
T9	465	1	0	0
T10	1653	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	22841	0	0
T1	10974	6	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	6	0	0
T5	216800	102	0	0
T6	151210	45	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	6	0	0
T10	55167	1	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56860090	22841	0	0
T1	10974	6	0	0
T2	17138	2	0	0
T3	15399	2	0	0
T4	12111	6	0	0
T5	216800	102	0	0
T6	151210	45	0	0
T7	6926	1	0	0
T8	9746	2	0	0
T9	15554	6	0	0
T10	55167	1	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	258	0	0
T19	20941	2	0	0
T20	662	0	0	0
T21	203	0	0	0
T22	258	0	0	0
T23	732	0	0	0
T24	3682	0	0	0
T34	303	0	0	0
T40	7090	0	0	0
T64	527	0	0	0
T65	0	1	0	0
T67	314	0	0	0
T72	0	2	0	0
T73	0	4	0	0
T76	0	6	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0
T91	0	1	0	0
T129	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	9325	0	0
T1	327	2	0	0
T2	512	2	0	0
T3	460	2	0	0
T4	361	2	0	0
T5	6518	27	0	0
T6	4585	16	0	0
T7	206	1	0	0
T8	290	2	0	0
T9	465	2	0	0
T10	1653	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	22841	0	0
T1	2634	6	0	0
T2	4112	2	0	0
T3	3694	2	0	0
T4	2906	6	0	0
T5	52029	102	0	0
T6	36288	45	0	0
T7	1660	1	0	0
T8	2338	2	0	0
T9	3731	6	0	0
T10	13238	1	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	22841	0	0
T1	2634	6	0	0
T2	4112	2	0	0
T3	3694	2	0	0
T4	2906	6	0	0
T5	52029	102	0	0
T6	36288	45	0	0
T7	1660	1	0	0
T8	2338	2	0	0
T9	3731	6	0	0
T10	13238	1	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12113777	22841	0	0
T1	2488	6	0	0
T2	3998	2	0	0
T3	3556	2	0	0
T4	2759	6	0	0
T5	48532	102	0	0
T6	32679	45	0	0
T7	1643	1	0	0
T8	2247	2	0	0
T9	3539	6	0	0
T10	13173	1	0	0