Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T19
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T19
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T10,T19
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T19,T38
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T19,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T19,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T19,T39
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T19,T39
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13645948	14447	0	0
gen_assertions[0].RstEnOn_A	13645948	1150	0	0
gen_assertions[0].RstNOff_A	13645948	14447	0	0
gen_assertions[0].RstNOn_A	13645948	1150	0	0
gen_assertions[1].RstEnOff_A	54583979	13152	0	0
gen_assertions[1].RstEnOn_A	54583979	1107	0	0
gen_assertions[1].RstNOff_A	54583979	13152	0	0
gen_assertions[1].RstNOn_A	54583979	1107	0	0
gen_assertions[2].RstEnOff_A	27292865	13197	0	0
gen_assertions[2].RstEnOn_A	27292865	1077	0	0
gen_assertions[2].RstNOff_A	27292865	13197	0	0
gen_assertions[2].RstNOn_A	27292865	1077	0	0
gen_assertions[3].RstEnOff_A	27293044	13246	0	0
gen_assertions[3].RstEnOn_A	27293044	1111	0	0
gen_assertions[3].RstNOff_A	27293044	13246	0	0
gen_assertions[3].RstNOn_A	27293044	1111	0	0
gen_assertions[4].RstEnOff_A	1723402	22704	0	0
gen_assertions[4].RstEnOn_A	1723402	1144	0	0
gen_assertions[4].RstNOff_A	1723402	22704	0	0
gen_assertions[4].RstNOn_A	1723402	1144	0	0
gen_assertions[5].RstEnOff_A	13645948	14693	0	0
gen_assertions[5].RstEnOn_A	13645948	1213	0	0
gen_assertions[5].RstNOff_A	13645948	14693	0	0
gen_assertions[5].RstNOn_A	13645948	1213	0	0
gen_assertions[6].RstEnOff_A	13645948	14743	0	0
gen_assertions[6].RstEnOn_A	13645948	1261	0	0
gen_assertions[6].RstNOff_A	13645948	14743	0	0
gen_assertions[6].RstNOn_A	13645948	1261	0	0
gen_assertions[7].RstEnOff_A	13645948	14796	0	0
gen_assertions[7].RstEnOn_A	13645948	1309	0	0
gen_assertions[7].RstNOff_A	13645948	14796	0	0
gen_assertions[7].RstNOn_A	13645948	1309	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14447	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	8	0	0
T11	0	5	0	0
T19	0	185	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1150	0	0
T10	13238	8	0	0
T11	1957	4	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	23	0	0
T20	5310	2	0	0
T21	1634	0	0	0
T22	2070	2	0	0
T23	5845	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T39	0	6	0	0
T40	56606	0	0	0
T67	0	1	0	0
T68	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14447	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	8	0	0
T11	0	5	0	0
T19	0	185	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1150	0	0
T10	13238	8	0	0
T11	1957	4	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	23	0	0
T20	5310	2	0	0
T21	1634	0	0	0
T22	2070	2	0	0
T23	5845	0	0	0
T34	0	3	0	0
T35	0	2	0	0
T39	0	6	0	0
T40	56606	0	0	0
T67	0	1	0	0
T68	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54583979	13152	0	0
T1	10538	4	0	0
T2	16452	0	0	0
T3	14782	0	0	0
T4	11622	4	0	0
T5	208109	66	0	0
T6	145140	25	0	0
T7	6648	0	0	0
T8	9357	0	0	0
T9	14936	4	0	0
T10	52959	8	0	0
T11	0	5	0	0
T19	0	175	0	0
T20	0	16	0	0
T21	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54583979	1107	0	0
T10	52959	8	0	0
T11	7832	2	0	0
T12	9606	0	0	0
T13	10213	0	0	0
T19	661482	25	0	0
T20	21246	1	0	0
T21	6541	0	0	0
T22	8290	3	0	0
T23	23396	0	0	0
T34	0	2	0	0
T39	0	6	0	0
T40	226368	0	0	0
T49	0	7	0	0
T69	0	4	0	0
T70	0	6	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54583979	13152	0	0
T1	10538	4	0	0
T2	16452	0	0	0
T3	14782	0	0	0
T4	11622	4	0	0
T5	208109	66	0	0
T6	145140	25	0	0
T7	6648	0	0	0
T8	9357	0	0	0
T9	14936	4	0	0
T10	52959	8	0	0
T11	0	5	0	0
T19	0	175	0	0
T20	0	16	0	0
T21	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54583979	1107	0	0
T10	52959	8	0	0
T11	7832	2	0	0
T12	9606	0	0	0
T13	10213	0	0	0
T19	661482	25	0	0
T20	21246	1	0	0
T21	6541	0	0	0
T22	8290	3	0	0
T23	23396	0	0	0
T34	0	2	0	0
T39	0	6	0	0
T40	226368	0	0	0
T49	0	7	0	0
T69	0	4	0	0
T70	0	6	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27292865	13197	0	0
T1	5270	4	0	0
T2	8225	0	0	0
T3	7391	0	0	0
T4	5813	5	0	0
T5	104060	66	0	0
T6	72567	25	0	0
T7	3323	0	0	0
T8	4679	0	0	0
T9	7466	4	0	0
T10	26480	10	0	0
T11	0	5	0	0
T19	0	177	0	0
T20	0	16	0	0
T21	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27292865	1077	0	0
T4	5813	1	0	0
T5	104060	0	0	0
T6	72567	0	0	0
T7	3323	0	0	0
T8	4679	0	0	0
T9	7466	0	0	0
T10	26480	10	0	0
T11	3915	0	0	0
T12	4802	0	0	0
T13	5106	0	0	0
T19	0	29	0	0
T34	0	1	0	0
T39	0	6	0	0
T49	0	8	0	0
T53	0	1	0	0
T69	0	1	0	0
T70	0	8	0	0
T71	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27292865	13197	0	0
T1	5270	4	0	0
T2	8225	0	0	0
T3	7391	0	0	0
T4	5813	5	0	0
T5	104060	66	0	0
T6	72567	25	0	0
T7	3323	0	0	0
T8	4679	0	0	0
T9	7466	4	0	0
T10	26480	10	0	0
T11	0	5	0	0
T19	0	177	0	0
T20	0	16	0	0
T21	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27292865	1077	0	0
T4	5813	1	0	0
T5	104060	0	0	0
T6	72567	0	0	0
T7	3323	0	0	0
T8	4679	0	0	0
T9	7466	0	0	0
T10	26480	10	0	0
T11	3915	0	0	0
T12	4802	0	0	0
T13	5106	0	0	0
T19	0	29	0	0
T34	0	1	0	0
T39	0	6	0	0
T49	0	8	0	0
T53	0	1	0	0
T69	0	1	0	0
T70	0	8	0	0
T71	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27293044	13246	0	0
T1	5267	4	0	0
T2	8226	0	0	0
T3	7391	0	0	0
T4	5813	4	0	0
T5	104060	66	0	0
T6	72573	25	0	0
T7	3324	0	0	0
T8	4678	0	0	0
T9	7465	4	0	0
T10	26480	10	0	0
T11	0	5	0	0
T19	0	170	0	0
T20	0	16	0	0
T21	0	2	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27293044	1111	0	0
T10	26480	10	0	0
T11	3916	0	0	0
T12	4803	0	0	0
T13	5105	0	0	0
T19	330785	20	0	0
T20	10623	0	0	0
T21	3269	0	0	0
T22	4143	0	0	0
T23	11689	0	0	0
T38	0	1	0	0
T39	0	8	0	0
T40	113196	0	0	0
T49	0	11	0	0
T53	0	1	0	0
T70	0	8	0	0
T72	0	8	0	0
T73	0	18	0	0
T74	0	9	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27293044	13246	0	0
T1	5267	4	0	0
T2	8226	0	0	0
T3	7391	0	0	0
T4	5813	4	0	0
T5	104060	66	0	0
T6	72573	25	0	0
T7	3324	0	0	0
T8	4678	0	0	0
T9	7465	4	0	0
T10	26480	10	0	0
T11	0	5	0	0
T19	0	170	0	0
T20	0	16	0	0
T21	0	2	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27293044	1111	0	0
T10	26480	10	0	0
T11	3916	0	0	0
T12	4803	0	0	0
T13	5105	0	0	0
T19	330785	20	0	0
T20	10623	0	0	0
T21	3269	0	0	0
T22	4143	0	0	0
T23	11689	0	0	0
T38	0	1	0	0
T39	0	8	0	0
T40	113196	0	0	0
T49	0	11	0	0
T53	0	1	0	0
T70	0	8	0	0
T72	0	8	0	0
T73	0	18	0	0
T74	0	9	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	22704	0	0
T1	327	5	0	0
T2	512	2	0	0
T3	460	2	0	0
T4	361	6	0	0
T5	6518	96	0	0
T6	4585	45	0	0
T7	206	1	0	0
T8	290	2	0	0
T9	465	6	0	0
T10	1653	13	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	1144	0	0
T10	1653	12	0	0
T11	244	0	0	0
T12	298	0	0	0
T13	319	0	0	0
T19	20941	22	0	0
T20	662	0	0	0
T21	203	0	0	0
T22	258	0	0	0
T23	732	0	0	0
T39	0	10	0	0
T40	7090	0	0	0
T49	0	10	0	0
T53	0	1	0	0
T70	0	10	0	0
T72	0	9	0	0
T73	0	21	0	0
T74	0	10	0	0
T75	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	22704	0	0
T1	327	5	0	0
T2	512	2	0	0
T3	460	2	0	0
T4	361	6	0	0
T5	6518	96	0	0
T6	4585	45	0	0
T7	206	1	0	0
T8	290	2	0	0
T9	465	6	0	0
T10	1653	13	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1723402	1144	0	0
T10	1653	12	0	0
T11	244	0	0	0
T12	298	0	0	0
T13	319	0	0	0
T19	20941	22	0	0
T20	662	0	0	0
T21	203	0	0	0
T22	258	0	0	0
T23	732	0	0	0
T39	0	10	0	0
T40	7090	0	0	0
T49	0	10	0	0
T53	0	1	0	0
T70	0	10	0	0
T72	0	9	0	0
T73	0	21	0	0
T74	0	10	0	0
T75	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14693	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	13	0	0
T11	0	5	0	0
T19	0	188	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1213	0	0
T10	13238	13	0	0
T11	1957	0	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	25	0	0
T20	5310	0	0	0
T21	1634	0	0	0
T22	2070	0	0	0
T23	5845	0	0	0
T39	0	11	0	0
T40	56606	0	0	0
T49	0	12	0	0
T66	0	1	0	0
T70	0	11	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	0	13	0	0
T76	0	19	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14693	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	13	0	0
T11	0	5	0	0
T19	0	188	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1213	0	0
T10	13238	13	0	0
T11	1957	0	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	25	0	0
T20	5310	0	0	0
T21	1634	0	0	0
T22	2070	0	0	0
T23	5845	0	0	0
T39	0	11	0	0
T40	56606	0	0	0
T49	0	12	0	0
T66	0	1	0	0
T70	0	11	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	0	13	0	0
T76	0	19	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14743	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	15	0	0
T11	0	5	0	0
T19	0	184	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1261	0	0
T10	13238	15	0	0
T11	1957	0	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	21	0	0
T20	5310	0	0	0
T21	1634	0	0	0
T22	2070	0	0	0
T23	5845	0	0	0
T39	0	12	0	0
T40	56606	0	0	0
T49	0	14	0	0
T66	0	1	0	0
T70	0	9	0	0
T72	0	8	0	0
T73	0	18	0	0
T74	0	13	0	0
T77	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14743	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	15	0	0
T11	0	5	0	0
T19	0	184	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1261	0	0
T10	13238	15	0	0
T11	1957	0	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	21	0	0
T20	5310	0	0	0
T21	1634	0	0	0
T22	2070	0	0	0
T23	5845	0	0	0
T39	0	12	0	0
T40	56606	0	0	0
T49	0	14	0	0
T66	0	1	0	0
T70	0	9	0	0
T72	0	8	0	0
T73	0	18	0	0
T74	0	13	0	0
T77	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14796	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	15	0	0
T11	0	5	0	0
T19	0	183	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1309	0	0
T10	13238	15	0	0
T11	1957	0	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	19	0	0
T20	5310	0	0	0
T21	1634	0	0	0
T22	2070	0	0	0
T23	5845	0	0	0
T39	0	12	0	0
T40	56606	0	0	0
T49	0	16	0	0
T70	0	13	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	0	16	0	0
T76	0	29	0	0
T78	0	14	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	14796	0	0
T1	2634	4	0	0
T2	4112	0	0	0
T3	3694	0	0	0
T4	2906	4	0	0
T5	52029	75	0	0
T6	36288	29	0	0
T7	1660	0	0	0
T8	2338	0	0	0
T9	3731	4	0	0
T10	13238	15	0	0
T11	0	5	0	0
T19	0	183	0	0
T20	0	17	0	0
T21	0	2	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13645948	1309	0	0
T10	13238	15	0	0
T11	1957	0	0	0
T12	2400	0	0	0
T13	2551	0	0	0
T19	165372	19	0	0
T20	5310	0	0	0
T21	1634	0	0	0
T22	2070	0	0	0
T23	5845	0	0	0
T39	0	12	0	0
T40	56606	0	0	0
T49	0	16	0	0
T70	0	13	0	0
T72	0	10	0	0
T73	0	20	0	0
T74	0	16	0	0
T76	0	29	0	0
T78	0	14	0	0