Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12806137	7317	0	0
alert_regwen_rd_A	12806137	4441	0	0
cpu_regwen_rd_A	12806137	4508	0	0
sw_rst_ctrl_n_0_rd_A	12806137	9999	0	0
sw_rst_ctrl_n_1_rd_A	12806137	9916	0	0
sw_rst_ctrl_n_2_rd_A	12806137	9696	0	0
sw_rst_ctrl_n_3_rd_A	12806137	9891	0	0
sw_rst_ctrl_n_4_rd_A	12806137	9880	0	0
sw_rst_ctrl_n_5_rd_A	12806137	9746	0	0
sw_rst_ctrl_n_6_rd_A	12806137	10002	0	0
sw_rst_ctrl_n_7_rd_A	12806137	9939	0	0
sw_rst_regwen_0_rd_A	12806137	4992	0	0
sw_rst_regwen_1_rd_A	12806137	5221	0	0
sw_rst_regwen_2_rd_A	12806137	5263	0	0
sw_rst_regwen_3_rd_A	12806137	5000	0	0
sw_rst_regwen_4_rd_A	12806137	4978	0	0
sw_rst_regwen_5_rd_A	12806137	5152	0	0
sw_rst_regwen_6_rd_A	12806137	4932	0	0
sw_rst_regwen_7_rd_A	12806137	4889	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	7317	0	0
T54	2748	174	0	0
T55	4936	22	0	0
T56	10544	339	0	0
T60	2425	16	0	0
T81	10815	1	0	0
T82	10972	609	0	0
T83	3860	52	0	0
T84	2658	150	0	0
T85	4819	32	0	0
T113	10453	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	4441	0	0
T6	32679	54	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	0	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T72	0	148	0	0
T76	0	194	0	0
T91	0	43	0	0
T99	0	339	0	0
T101	0	82	0	0
T124	0	46	0	0
T125	0	35	0	0
T126	0	259	0	0
T127	0	239	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	4508	0	0
T6	32679	50	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	0	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T72	0	153	0	0
T76	0	218	0	0
T91	0	32	0	0
T99	0	317	0	0
T101	0	84	0	0
T124	0	96	0	0
T125	0	41	0	0
T126	0	283	0	0
T127	0	204	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	9999	0	0
T6	32679	36	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	214	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	12	0	0
T39	0	176	0	0
T49	0	162	0	0
T53	0	13	0	0
T67	0	9	0	0
T72	0	242	0	0
T74	0	164	0	0
T76	0	495	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	9916	0	0
T6	32679	58	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	221	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	9	0	0
T39	0	204	0	0
T49	0	150	0	0
T53	0	5	0	0
T67	0	1	0	0
T72	0	238	0	0
T74	0	130	0	0
T76	0	545	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	9696	0	0
T6	32679	33	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	200	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	8	0	0
T39	0	215	0	0
T49	0	136	0	0
T53	0	15	0	0
T67	0	14	0	0
T72	0	211	0	0
T74	0	133	0	0
T76	0	565	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	9891	0	0
T6	32679	56	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	167	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	23	0	0
T39	0	199	0	0
T49	0	111	0	0
T53	0	7	0	0
T67	0	12	0	0
T72	0	256	0	0
T74	0	93	0	0
T76	0	597	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	9880	0	0
T6	32679	65	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	233	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	11	0	0
T39	0	197	0	0
T49	0	119	0	0
T53	0	16	0	0
T67	0	18	0	0
T72	0	272	0	0
T74	0	126	0	0
T76	0	516	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	9746	0	0
T6	32679	41	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	236	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	18	0	0
T39	0	198	0	0
T49	0	111	0	0
T53	0	6	0	0
T67	0	5	0	0
T72	0	259	0	0
T74	0	154	0	0
T76	0	560	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	10002	0	0
T6	32679	54	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	251	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	18	0	0
T39	0	222	0	0
T49	0	121	0	0
T53	0	8	0	0
T67	0	2	0	0
T72	0	274	0	0
T74	0	157	0	0
T76	0	655	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	9939	0	0
T6	32679	71	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	247	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	7	0	0
T39	0	194	0	0
T49	0	149	0	0
T53	0	10	0	0
T67	0	9	0	0
T72	0	227	0	0
T74	0	97	0	0
T76	0	590	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	4992	0	0
T6	32679	63	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	25	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	3	0	0
T39	0	42	0	0
T49	0	4	0	0
T53	0	8	0	0
T72	0	183	0	0
T74	0	29	0	0
T76	0	232	0	0
T128	0	1	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	5221	0	0
T6	32679	70	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	38	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	11	0	0
T39	0	27	0	0
T49	0	16	0	0
T53	0	6	0	0
T72	0	168	0	0
T74	0	15	0	0
T76	0	210	0	0
T128	0	26	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	5263	0	0
T6	32679	53	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	33	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	8	0	0
T39	0	16	0	0
T49	0	36	0	0
T53	0	14	0	0
T72	0	148	0	0
T74	0	20	0	0
T76	0	210	0	0
T128	0	11	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	5000	0	0
T6	32679	30	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	46	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	12	0	0
T39	0	29	0	0
T49	0	23	0	0
T53	0	9	0	0
T72	0	171	0	0
T74	0	25	0	0
T76	0	203	0	0
T128	0	12	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	4978	0	0
T6	32679	54	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	40	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	7	0	0
T39	0	30	0	0
T49	0	11	0	0
T53	0	8	0	0
T72	0	204	0	0
T74	0	7	0	0
T76	0	217	0	0
T128	0	8	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	5152	0	0
T6	32679	60	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	53	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	8	0	0
T39	0	30	0	0
T49	0	25	0	0
T53	0	2	0	0
T72	0	221	0	0
T74	0	25	0	0
T76	0	202	0	0
T128	0	16	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	4932	0	0
T6	32679	66	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	23	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	1	0	0
T39	0	39	0	0
T49	0	13	0	0
T53	0	7	0	0
T72	0	166	0	0
T74	0	19	0	0
T76	0	208	0	0
T128	0	15	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12806137	4889	0	0
T6	32679	44	0	0
T7	1643	0	0	0
T8	2247	0	0	0
T9	3539	0	0	0
T10	13173	18	0	0
T11	1630	0	0	0
T12	2238	0	0	0
T13	2486	0	0	0
T19	146938	0	0	0
T20	4165	0	0	0
T38	0	3	0	0
T39	0	27	0	0
T49	0	30	0	0
T53	0	8	0	0
T72	0	194	0	0
T74	0	5	0	0
T76	0	218	0	0
T128	0	25	0	0