Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	645952	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

387304

1

T1

344

T2

356

T4

9400

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	550935	1			T1	443		T2	475		T4	13779
values[0x0]	241181	1			T1	188		T2	218		T4	5601
values[0x1]	241140	1			T1	209		T2	211		T4	5740

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	542722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

490534

1

T1

417

T2

440

T4

11954

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4938	1			T4	95		T7	4		T10	18
valid_sources[0x01]	3564	1			T4	80		T5	1		T7	1
valid_sources[0x02]	3360	1			T4	116		T5	3		T7	4
valid_sources[0x03]	4343	1			T1	1		T4	104		T5	1
valid_sources[0x04]	3563	1			T1	2		T4	93		T5	1
valid_sources[0x05]	3277	1			T4	88		T7	2		T8	2
valid_sources[0x06]	3326	1			T4	85		T5	2		T7	1
valid_sources[0x07]	4408	1			T4	92		T5	1		T7	8
valid_sources[0x08]	3859	1			T1	18		T4	88		T5	2
valid_sources[0x09]	3786	1			T4	92		T5	2		T7	5
valid_sources[0x0a]	3419	1			T4	91		T7	2		T12	2
valid_sources[0x0b]	4176	1			T4	100		T7	3		T8	5
valid_sources[0x0c]	6830	1			T4	93		T5	1		T7	5
valid_sources[0x0d]	3625	1			T1	8		T4	113		T7	6
valid_sources[0x0e]	3208	1			T1	19		T4	94		T7	5
valid_sources[0x0f]	3842	1			T1	28		T4	104		T7	4
valid_sources[0x10]	4182	1			T4	91		T5	2		T7	4
valid_sources[0x11]	3742	1			T4	95		T5	1		T7	3
valid_sources[0x12]	3757	1			T4	90		T5	2		T7	3
valid_sources[0x13]	3277	1			T4	110		T7	2		T10	26
valid_sources[0x14]	3820	1			T1	1		T4	105		T7	7
valid_sources[0x15]	3783	1			T4	95		T5	2		T7	1
valid_sources[0x16]	3754	1			T1	5		T4	85		T7	4
valid_sources[0x17]	3498	1			T1	18		T4	110		T7	2
valid_sources[0x18]	3653	1			T4	79		T5	2		T7	3
valid_sources[0x19]	3361	1			T1	28		T4	104		T7	3
valid_sources[0x1a]	3838	1			T4	96		T5	1		T7	4
valid_sources[0x1b]	3372	1			T1	7		T4	90		T7	4
valid_sources[0x1c]	3214	1			T1	4		T4	98		T7	3
valid_sources[0x1d]	5417	1			T1	17		T4	105		T5	1
valid_sources[0x1e]	4329	1			T1	4		T4	102		T7	2
valid_sources[0x1f]	3554	1			T4	81		T5	1		T7	2
valid_sources[0x20]	3993	1			T1	13		T4	90		T7	2
valid_sources[0x21]	3331	1			T1	9		T4	93		T5	1
valid_sources[0x22]	4229	1			T1	6		T4	102		T5	3
valid_sources[0x23]	3499	1			T1	2		T4	111		T7	8
valid_sources[0x24]	4056	1			T4	119		T5	1		T7	3
valid_sources[0x25]	3788	1			T1	6		T4	112		T5	1
valid_sources[0x26]	3410	1			T4	128		T5	1		T7	4
valid_sources[0x27]	3373	1			T1	9		T4	106		T7	1
valid_sources[0x28]	4177	1			T1	11		T4	98		T7	3
valid_sources[0x29]	7052	1			T4	101		T7	4		T8	1
valid_sources[0x2a]	4734	1			T1	21		T4	95		T5	1
valid_sources[0x2b]	3834	1			T1	7		T4	105		T5	2
valid_sources[0x2c]	4115	1			T4	102		T7	8		T8	5
valid_sources[0x2d]	3313	1			T1	6		T4	117		T7	4
valid_sources[0x2e]	3877	1			T1	3		T4	105		T7	4
valid_sources[0x2f]	3188	1			T4	92		T7	3		T10	13
valid_sources[0x30]	3401	1			T4	101		T7	6		T8	4
valid_sources[0x31]	3553	1			T4	89		T5	1		T7	3
valid_sources[0x32]	3735	1			T4	104		T7	3		T8	3
valid_sources[0x33]	3084	1			T1	13		T4	102		T7	3
valid_sources[0x34]	5409	1			T1	5		T4	109		T7	4
valid_sources[0x35]	3922	1			T1	2		T4	112		T7	5
valid_sources[0x36]	7908	1			T1	1		T4	86		T7	4
valid_sources[0x37]	3747	1			T4	95		T5	1		T7	4
valid_sources[0x38]	4308	1			T4	102		T7	2		T13	14
valid_sources[0x39]	3569	1			T4	104		T7	3		T12	19
valid_sources[0x3a]	3473	1			T4	100		T5	2		T7	2
valid_sources[0x3b]	3332	1			T4	94		T5	2		T7	2
valid_sources[0x3c]	4173	1			T4	100		T7	4		T12	25
valid_sources[0x3d]	7024	1			T4	94		T7	2		T8	5
valid_sources[0x3e]	3853	1			T4	87		T7	2		T8	3
valid_sources[0x3f]	4537	1			T4	96		T7	3		T13	6
valid_sources[0x40]	4007	1			T1	10		T4	87		T7	2
valid_sources[0x41]	3655	1			T4	97		T7	5		T8	6
valid_sources[0x42]	6587	1			T4	130		T7	1		T10	10
valid_sources[0x43]	3830	1			T4	105		T7	3		T10	10
valid_sources[0x44]	4294	1			T1	5		T4	116		T7	2
valid_sources[0x45]	3741	1			T4	87		T7	4		T10	4
valid_sources[0x46]	3434	1			T4	97		T5	2		T7	4
valid_sources[0x47]	3359	1			T4	80		T5	1		T7	2
valid_sources[0x48]	4229	1			T1	18		T4	103		T5	1
valid_sources[0x49]	3592	1			T1	2		T4	78		T5	2
valid_sources[0x4a]	5208	1			T4	97		T7	5		T12	6
valid_sources[0x4b]	3626	1			T4	110		T5	1		T7	2
valid_sources[0x4c]	4114	1			T1	3		T4	105		T7	2
valid_sources[0x4d]	3358	1			T4	113		T7	4		T8	5
valid_sources[0x4e]	3145	1			T4	99		T7	6		T17	4
valid_sources[0x4f]	3168	1			T4	101		T7	2		T8	1
valid_sources[0x50]	3427	1			T1	22		T4	103		T7	1
valid_sources[0x51]	4997	1			T4	90		T7	3		T10	2
valid_sources[0x52]	3418	1			T4	103		T5	2		T7	2
valid_sources[0x53]	4372	1			T1	4		T4	114		T5	2
valid_sources[0x54]	4092	1			T4	99		T7	6		T8	3
valid_sources[0x55]	3596	1			T4	97		T5	4		T7	3
valid_sources[0x56]	3693	1			T4	96		T5	2		T7	3
valid_sources[0x57]	4327	1			T4	90		T7	2		T10	3
valid_sources[0x58]	4753	1			T1	18		T4	107		T5	2
valid_sources[0x59]	3791	1			T4	86		T7	3		T13	2
valid_sources[0x5a]	3838	1			T4	111		T5	1		T7	1
valid_sources[0x5b]	3763	1			T4	90		T7	2		T8	1
valid_sources[0x5c]	3754	1			T1	11		T4	103		T7	4
valid_sources[0x5d]	3815	1			T4	83		T5	2		T7	11
valid_sources[0x5e]	3690	1			T1	4		T4	124		T7	7
valid_sources[0x5f]	3882	1			T4	103		T5	1		T7	2
valid_sources[0x60]	3411	1			T4	93		T5	1		T7	3
valid_sources[0x61]	3610	1			T4	94		T5	2		T7	7
valid_sources[0x62]	6426	1			T1	1		T4	108		T7	3
valid_sources[0x63]	4003	1			T1	5		T4	86		T7	2
valid_sources[0x64]	3393	1			T1	6		T4	105		T7	6
valid_sources[0x65]	3413	1			T1	6		T4	114		T7	6
valid_sources[0x66]	3717	1			T4	102		T5	1		T7	2
valid_sources[0x67]	3714	1			T1	25		T4	97		T7	5
valid_sources[0x68]	4228	1			T4	101		T7	6		T13	11
valid_sources[0x69]	4299	1			T4	81		T5	4		T7	4
valid_sources[0x6a]	3038	1			T1	1		T4	80		T7	4
valid_sources[0x6b]	3502	1			T4	98		T5	1		T7	2
valid_sources[0x6c]	3453	1			T1	13		T4	96		T10	7
valid_sources[0x6d]	3338	1			T4	104		T7	4		T8	2
valid_sources[0x6e]	7720	1			T4	103		T5	1		T7	3
valid_sources[0x6f]	3642	1			T1	4		T4	92		T5	1
valid_sources[0x70]	4427	1			T1	5		T4	84		T5	1
valid_sources[0x71]	4069	1			T4	87		T5	2		T7	4
valid_sources[0x72]	3447	1			T1	3		T4	80		T5	1
valid_sources[0x73]	3696	1			T1	1		T4	76		T7	4
valid_sources[0x74]	4309	1			T4	95		T5	1		T7	3
valid_sources[0x75]	3991	1			T4	94		T7	1		T8	2
valid_sources[0x76]	4635	1			T4	97		T7	5		T8	5
valid_sources[0x77]	3908	1			T4	90		T7	5		T10	17
valid_sources[0x78]	3867	1			T4	113		T7	6		T12	9
valid_sources[0x79]	3918	1			T1	23		T4	88		T7	2
valid_sources[0x7a]	3694	1			T1	11		T4	91		T7	5
valid_sources[0x7b]	3488	1			T4	105		T5	2		T7	7
valid_sources[0x7c]	3547	1			T1	6		T4	102		T7	3
valid_sources[0x7d]	3867	1			T4	99		T7	3		T8	2
valid_sources[0x7e]	3456	1			T1	3		T4	95		T5	2
valid_sources[0x7f]	5436	1			T4	102		T5	1		T7	2
valid_sources[0x80]	4926	1			T2	904		T4	92		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

258234

1

T1

250

T2

238

T4

6500

values[0x0]

all_enables

biggest_size

84064

1

T1

62

T2

83

T4

1899

values[0x1]

all_enables

biggest_size

45006

1

T1

32

T2

35

T4

1001