Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T6

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11564529	13767	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11564529	126977	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11564529	6969594	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11564529	202485	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11564529	13767	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11564529	126977	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11564529	6969594	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11564529	202485	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	13767	0	0
T4	349616	310	0	0
T5	2094	9	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	4	0	0
T9	1904	0	0	0
T10	30760	31	0	0
T11	2621	20	0	0
T12	27234	39	0	0
T13	0	75	0	0
T14	0	4	0	0
T17	1628	0	0	0
T29	0	4	0	0
T33	0	13	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	126977	0	0
T4	349616	2847	0	0
T5	2094	81	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	38	0	0
T9	1904	0	0	0
T10	30760	283	0	0
T11	2621	180	0	0
T12	27234	351	0	0
T13	0	702	0	0
T14	0	38	0	0
T17	1628	0	0	0
T29	0	37	0	0
T33	0	117	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	6969594	0	0
T1	7455	6809	0	0
T2	10980	10363	0	0
T3	5674	571	0	0
T4	349616	282104	0	0
T5	2094	1319	0	0
T6	5096	562	0	0
T7	2827	2258	0	0
T8	5021	4098	0	0
T9	1904	1330	0	0
T10	30760	24821	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	202485	0	0
T4	349616	4606	0	0
T5	2094	132	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	51	0	0
T9	1904	0	0	0
T10	30760	474	0	0
T11	2621	303	0	0
T12	27234	562	0	0
T13	0	1091	0	0
T14	0	64	0	0
T17	1628	0	0	0
T29	0	51	0	0
T33	0	196	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	13767	0	0
T4	349616	310	0	0
T5	2094	9	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	4	0	0
T9	1904	0	0	0
T10	30760	31	0	0
T11	2621	20	0	0
T12	27234	39	0	0
T13	0	75	0	0
T14	0	4	0	0
T17	1628	0	0	0
T29	0	4	0	0
T33	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	126977	0	0
T4	349616	2847	0	0
T5	2094	81	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	38	0	0
T9	1904	0	0	0
T10	30760	283	0	0
T11	2621	180	0	0
T12	27234	351	0	0
T13	0	702	0	0
T14	0	38	0	0
T17	1628	0	0	0
T29	0	37	0	0
T33	0	117	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	6969594	0	0
T1	7455	6809	0	0
T2	10980	10363	0	0
T3	5674	571	0	0
T4	349616	282104	0	0
T5	2094	1319	0	0
T6	5096	562	0	0
T7	2827	2258	0	0
T8	5021	4098	0	0
T9	1904	1330	0	0
T10	30760	24821	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	202485	0	0
T4	349616	4606	0	0
T5	2094	132	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	51	0	0
T9	1904	0	0	0
T10	30760	474	0	0
T11	2621	303	0	0
T12	27234	562	0	0
T13	0	1091	0	0
T14	0	64	0	0
T17	1628	0	0	0
T29	0	51	0	0
T33	0	196	0	0