Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T8,T10
0	1	Covered	T4,T8,T10
1	0	Covered	T4,T10,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T4,T8,T10
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54634178	8576	0	0
CascadeEffAonToRstPorAboveRise_A	54634178	8576	0	0
CascadeEffAonToRstPorIoAboveFall_A	52446464	8576	0	0
CascadeEffAonToRstPorIoAboveRise_A	52446464	8576	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26224169	8576	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26224169	8576	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13111695	8576	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13111695	8576	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26224382	8576	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26224382	8576	0	0
CascadeLcToLcAboveFall_A	54634178	22343	0	0
CascadeLcToLcAboveRise_A	54634178	22343	0	0
CascadeLcToLcAonAboveFall_A	1656710	22343	0	0
CascadeLcToLcAonAboveRise_A	1656710	22343	0	0
CascadeLcToLcShadowedAboveFall_A	54634178	22343	0	0
CascadeLcToLcShadowedAboveRise_A	54634178	22343	0	0
CascadePorToAonAboveFall_A	1656710	6652	0	0
CascadeSysToSysAboveFall_A	54634178	22343	0	0
CascadeSysToSysAboveRise_A	54634178	22343	0	0
ScanRstToAonRise_A	1656710	234	0	0
StablePorToAonRise_A	1656710	8576	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11564529	22343	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11564529	22343	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11564529	22343	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11564529	22343	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13111695	22343	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13111695	22343	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11564529	22343	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11564529	22343	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11564529	22343	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11564529	22343	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	8576	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	150	0	0
T5	11203	1	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	2	0	0
T9	8314	1	0	0
T10	144790	15	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	8576	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	150	0	0
T5	11203	1	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	2	0	0
T9	8314	1	0	0
T10	144790	15	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52446464	8576	0	0
T1	29896	1	0	0
T2	44092	1	0	0
T3	23350	8	0	0
T4	155687	150	0	0
T5	10755	1	0	0
T6	23331	8	0	0
T7	11672	1	0	0
T8	21631	2	0	0
T9	7981	1	0	0
T10	139008	15	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52446464	8576	0	0
T1	29896	1	0	0
T2	44092	1	0	0
T3	23350	8	0	0
T4	155687	150	0	0
T5	10755	1	0	0
T6	23331	8	0	0
T7	11672	1	0	0
T8	21631	2	0	0
T9	7981	1	0	0
T10	139008	15	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224169	8576	0	0
T1	14949	1	0	0
T2	22045	1	0	0
T3	11670	8	0	0
T4	778482	150	0	0
T5	5376	1	0	0
T6	11667	8	0	0
T7	5836	1	0	0
T8	10816	2	0	0
T9	3990	1	0	0
T10	69511	15	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224169	8576	0	0
T1	14949	1	0	0
T2	22045	1	0	0
T3	11670	8	0	0
T4	778482	150	0	0
T5	5376	1	0	0
T6	11667	8	0	0
T7	5836	1	0	0
T8	10816	2	0	0
T9	3990	1	0	0
T10	69511	15	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	8576	0	0
T1	7474	1	0	0
T2	11022	1	0	0
T3	5830	8	0	0
T4	389249	150	0	0
T5	2687	1	0	0
T6	5834	8	0	0
T7	2916	1	0	0
T8	5407	2	0	0
T9	1994	1	0	0
T10	34750	15	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	8576	0	0
T1	7474	1	0	0
T2	11022	1	0	0
T3	5830	8	0	0
T4	389249	150	0	0
T5	2687	1	0	0
T6	5834	8	0	0
T7	2916	1	0	0
T8	5407	2	0	0
T9	1994	1	0	0
T10	34750	15	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224382	8576	0	0
T1	14949	1	0	0
T2	22046	1	0	0
T3	11676	8	0	0
T4	778485	150	0	0
T5	5376	1	0	0
T6	11663	8	0	0
T7	5835	1	0	0
T8	10816	2	0	0
T9	3990	1	0	0
T10	69505	15	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224382	8576	0	0
T1	14949	1	0	0
T2	22046	1	0	0
T3	11676	8	0	0
T4	778485	150	0	0
T5	5376	1	0	0
T6	11663	8	0	0
T7	5835	1	0	0
T8	10816	2	0	0
T9	3990	1	0	0
T10	69505	15	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	22343	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	460	0	0
T5	11203	10	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	6	0	0
T9	8314	1	0	0
T10	144790	46	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	22343	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	460	0	0
T5	11203	10	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	6	0	0
T9	8314	1	0	0
T10	144790	46	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	22343	0	0
T1	933	1	0	0
T2	1377	1	0	0
T3	731	8	0	0
T4	49188	460	0	0
T5	335	10	0	0
T6	731	8	0	0
T7	364	1	0	0
T8	675	6	0	0
T9	248	1	0	0
T10	4381	46	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	22343	0	0
T1	933	1	0	0
T2	1377	1	0	0
T3	731	8	0	0
T4	49188	460	0	0
T5	335	10	0	0
T6	731	8	0	0
T7	364	1	0	0
T8	675	6	0	0
T9	248	1	0	0
T10	4381	46	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	22343	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	460	0	0
T5	11203	10	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	6	0	0
T9	8314	1	0	0
T10	144790	46	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	22343	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	460	0	0
T5	11203	10	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	6	0	0
T9	8314	1	0	0
T10	144790	46	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	6652	0	0
T1	933	1	0	0
T2	1377	1	0	0
T3	731	8	0	0
T4	49188	70	0	0
T5	335	1	0	0
T6	731	8	0	0
T7	364	1	0	0
T8	675	1	0	0
T9	248	1	0	0
T10	4381	4	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	22343	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	460	0	0
T5	11203	10	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	6	0	0
T9	8314	1	0	0
T10	144790	46	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54634178	22343	0	0
T1	31143	1	0	0
T2	45932	1	0	0
T3	24318	8	0	0
T4	162180	460	0	0
T5	11203	10	0	0
T6	24310	8	0	0
T7	12159	1	0	0
T8	22536	6	0	0
T9	8314	1	0	0
T10	144790	46	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	234	0	0
T4	49188	7	0	0
T5	335	0	0	0
T6	731	0	0	0
T7	364	0	0	0
T8	675	0	0	0
T9	248	0	0	0
T10	4381	0	0	0
T11	496	0	0	0
T12	4013	0	0	0
T17	204	0	0	0
T44	0	7	0	0
T64	0	1	0	0
T92	0	2	0	0
T93	0	7	0	0
T95	0	8	0	0
T105	0	1	0	0
T106	0	1	0	0
T136	0	3	0	0
T137	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	8576	0	0
T1	933	1	0	0
T2	1377	1	0	0
T3	731	8	0	0
T4	49188	150	0	0
T5	335	1	0	0
T6	731	8	0	0
T7	364	1	0	0
T8	675	2	0	0
T9	248	1	0	0
T10	4381	15	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	22343	0	0
T1	7474	1	0	0
T2	11022	1	0	0
T3	5830	8	0	0
T4	389249	460	0	0
T5	2687	10	0	0
T6	5834	8	0	0
T7	2916	1	0	0
T8	5407	6	0	0
T9	1994	1	0	0
T10	34750	46	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	22343	0	0
T1	7474	1	0	0
T2	11022	1	0	0
T3	5830	8	0	0
T4	389249	460	0	0
T5	2687	10	0	0
T6	5834	8	0	0
T7	2916	1	0	0
T8	5407	6	0	0
T9	1994	1	0	0
T10	34750	46	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11564529	22343	0	0
T1	7455	1	0	0
T2	10980	1	0	0
T3	5674	8	0	0
T4	349616	460	0	0
T5	2094	10	0	0
T6	5096	8	0	0
T7	2827	1	0	0
T8	5021	6	0	0
T9	1904	1	0	0
T10	30760	46	0	0