Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T4,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13111695	14702	0	0
gen_assertions[0].RstEnOn_A	13111695	1141	0	0
gen_assertions[0].RstNOff_A	13111695	14702	0	0
gen_assertions[0].RstNOn_A	13111695	1141	0	0
gen_assertions[1].RstEnOff_A	52446464	13388	0	0
gen_assertions[1].RstEnOn_A	52446464	1096	0	0
gen_assertions[1].RstNOff_A	52446464	13388	0	0
gen_assertions[1].RstNOn_A	52446464	1096	0	0
gen_assertions[2].RstEnOff_A	26224169	13420	0	0
gen_assertions[2].RstEnOn_A	26224169	1079	0	0
gen_assertions[2].RstNOff_A	26224169	13420	0	0
gen_assertions[2].RstNOn_A	26224169	1079	0	0
gen_assertions[3].RstEnOff_A	26224382	13495	0	0
gen_assertions[3].RstEnOn_A	26224382	1147	0	0
gen_assertions[3].RstNOff_A	26224382	13495	0	0
gen_assertions[3].RstNOn_A	26224382	1147	0	0
gen_assertions[4].RstEnOff_A	1656710	22128	0	0
gen_assertions[4].RstEnOn_A	1656710	1207	0	0
gen_assertions[4].RstNOff_A	1656710	22128	0	0
gen_assertions[4].RstNOn_A	1656710	1207	0	0
gen_assertions[5].RstEnOff_A	13111695	14981	0	0
gen_assertions[5].RstEnOn_A	13111695	1260	0	0
gen_assertions[5].RstNOff_A	13111695	14981	0	0
gen_assertions[5].RstNOn_A	13111695	1260	0	0
gen_assertions[6].RstEnOff_A	13111695	15004	0	0
gen_assertions[6].RstEnOn_A	13111695	1283	0	0
gen_assertions[6].RstNOff_A	13111695	15004	0	0
gen_assertions[6].RstNOn_A	13111695	1283	0	0
gen_assertions[7].RstEnOff_A	13111695	15028	0	0
gen_assertions[7].RstEnOn_A	13111695	1298	0	0
gen_assertions[7].RstNOff_A	13111695	15028	0	0
gen_assertions[7].RstNOn_A	13111695	1298	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	14702	0	0
T1	7474	3	0	0
T2	11022	3	0	0
T3	5830	0	0	0
T4	389249	349	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	4	0	0
T8	5407	4	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1141	0	0
T1	7474	3	0	0
T2	11022	3	0	0
T3	5830	0	0	0
T4	389249	40	0	0
T5	2687	4	0	0
T6	5834	0	0	0
T7	2916	4	0	0
T8	5407	0	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T11	0	12	0	0
T14	0	1	0	0
T31	0	8	0	0
T32	0	1	0	0
T33	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	14702	0	0
T1	7474	3	0	0
T2	11022	3	0	0
T3	5830	0	0	0
T4	389249	349	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	4	0	0
T8	5407	4	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1141	0	0
T1	7474	3	0	0
T2	11022	3	0	0
T3	5830	0	0	0
T4	389249	40	0	0
T5	2687	4	0	0
T6	5834	0	0	0
T7	2916	4	0	0
T8	5407	0	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T11	0	12	0	0
T14	0	1	0	0
T31	0	8	0	0
T32	0	1	0	0
T33	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52446464	13388	0	0
T1	29896	3	0	0
T2	44092	5	0	0
T3	23350	0	0	0
T4	155687	319	0	0
T5	10755	9	0	0
T6	23331	0	0	0
T7	11672	6	0	0
T8	21631	4	0	0
T9	7981	0	0	0
T10	139008	28	0	0
T11	0	18	0	0
T12	0	35	0	0
T13	0	67	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52446464	1096	0	0
T1	29896	3	0	0
T2	44092	5	0	0
T3	23350	0	0	0
T4	155687	42	0	0
T5	10755	2	0	0
T6	23331	0	0	0
T7	11672	6	0	0
T8	21631	0	0	0
T9	7981	0	0	0
T10	139008	0	0	0
T11	0	6	0	0
T31	0	7	0	0
T32	0	3	0	0
T93	0	22	0	0
T96	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52446464	13388	0	0
T1	29896	3	0	0
T2	44092	5	0	0
T3	23350	0	0	0
T4	155687	319	0	0
T5	10755	9	0	0
T6	23331	0	0	0
T7	11672	6	0	0
T8	21631	4	0	0
T9	7981	0	0	0
T10	139008	28	0	0
T11	0	18	0	0
T12	0	35	0	0
T13	0	67	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52446464	1096	0	0
T1	29896	3	0	0
T2	44092	5	0	0
T3	23350	0	0	0
T4	155687	42	0	0
T5	10755	2	0	0
T6	23331	0	0	0
T7	11672	6	0	0
T8	21631	0	0	0
T9	7981	0	0	0
T10	139008	0	0	0
T11	0	6	0	0
T31	0	7	0	0
T32	0	3	0	0
T93	0	22	0	0
T96	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224169	13420	0	0
T1	14949	5	0	0
T2	22045	3	0	0
T3	11670	0	0	0
T4	778482	312	0	0
T5	5376	9	0	0
T6	11667	0	0	0
T7	5836	6	0	0
T8	10816	4	0	0
T9	3990	0	0	0
T10	69511	28	0	0
T11	0	18	0	0
T12	0	35	0	0
T13	0	67	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224169	1079	0	0
T1	14949	5	0	0
T2	22045	3	0	0
T3	11670	0	0	0
T4	778482	36	0	0
T5	5376	1	0	0
T6	11667	0	0	0
T7	5836	6	0	0
T8	10816	0	0	0
T9	3990	0	0	0
T10	69511	0	0	0
T11	0	1	0	0
T31	0	8	0	0
T32	0	3	0	0
T93	0	23	0	0
T96	0	9	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224169	13420	0	0
T1	14949	5	0	0
T2	22045	3	0	0
T3	11670	0	0	0
T4	778482	312	0	0
T5	5376	9	0	0
T6	11667	0	0	0
T7	5836	6	0	0
T8	10816	4	0	0
T9	3990	0	0	0
T10	69511	28	0	0
T11	0	18	0	0
T12	0	35	0	0
T13	0	67	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224169	1079	0	0
T1	14949	5	0	0
T2	22045	3	0	0
T3	11670	0	0	0
T4	778482	36	0	0
T5	5376	1	0	0
T6	11667	0	0	0
T7	5836	6	0	0
T8	10816	0	0	0
T9	3990	0	0	0
T10	69511	0	0	0
T11	0	1	0	0
T31	0	8	0	0
T32	0	3	0	0
T93	0	23	0	0
T96	0	9	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224382	13495	0	0
T1	14949	6	0	0
T2	22046	9	0	0
T3	11676	0	0	0
T4	778485	316	0	0
T5	5376	9	0	0
T6	11663	0	0	0
T7	5835	8	0	0
T8	10816	4	0	0
T9	3990	0	0	0
T10	69505	28	0	0
T11	0	18	0	0
T12	0	35	0	0
T13	0	67	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224382	1147	0	0
T1	14949	6	0	0
T2	22046	9	0	0
T3	11676	0	0	0
T4	778485	40	0	0
T5	5376	0	0	0
T6	11663	0	0	0
T7	5835	8	0	0
T8	10816	0	0	0
T9	3990	0	0	0
T10	69505	0	0	0
T14	0	1	0	0
T31	0	7	0	0
T32	0	7	0	0
T93	0	21	0	0
T96	0	8	0	0
T97	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224382	13495	0	0
T1	14949	6	0	0
T2	22046	9	0	0
T3	11676	0	0	0
T4	778485	316	0	0
T5	5376	9	0	0
T6	11663	0	0	0
T7	5835	8	0	0
T8	10816	4	0	0
T9	3990	0	0	0
T10	69505	28	0	0
T11	0	18	0	0
T12	0	35	0	0
T13	0	67	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26224382	1147	0	0
T1	14949	6	0	0
T2	22046	9	0	0
T3	11676	0	0	0
T4	778485	40	0	0
T5	5376	0	0	0
T6	11663	0	0	0
T7	5835	8	0	0
T8	10816	0	0	0
T9	3990	0	0	0
T10	69505	0	0	0
T14	0	1	0	0
T31	0	7	0	0
T32	0	7	0	0
T93	0	21	0	0
T96	0	8	0	0
T97	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	22128	0	0
T1	933	9	0	0
T2	1377	9	0	0
T3	731	2	0	0
T4	49188	494	0	0
T5	335	9	0	0
T6	731	2	0	0
T7	364	10	0	0
T8	675	6	0	0
T9	248	1	0	0
T10	4381	46	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	1207	0	0
T1	933	8	0	0
T2	1377	8	0	0
T3	731	0	0	0
T4	49188	40	0	0
T5	335	0	0	0
T6	731	0	0	0
T7	364	9	0	0
T8	675	0	0	0
T9	248	0	0	0
T10	4381	0	0	0
T31	0	11	0	0
T32	0	8	0	0
T93	0	20	0	0
T95	0	14	0	0
T96	0	12	0	0
T97	0	10	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	22128	0	0
T1	933	9	0	0
T2	1377	9	0	0
T3	731	2	0	0
T4	49188	494	0	0
T5	335	9	0	0
T6	731	2	0	0
T7	364	10	0	0
T8	675	6	0	0
T9	248	1	0	0
T10	4381	46	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1656710	1207	0	0
T1	933	8	0	0
T2	1377	8	0	0
T3	731	0	0	0
T4	49188	40	0	0
T5	335	0	0	0
T6	731	0	0	0
T7	364	9	0	0
T8	675	0	0	0
T9	248	0	0	0
T10	4381	0	0	0
T31	0	11	0	0
T32	0	8	0	0
T93	0	20	0	0
T95	0	14	0	0
T96	0	12	0	0
T97	0	10	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	14981	0	0
T1	7474	9	0	0
T2	11022	9	0	0
T3	5830	0	0	0
T4	389249	348	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	10	0	0
T8	5407	5	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1260	0	0
T1	7474	9	0	0
T2	11022	9	0	0
T3	5830	0	0	0
T4	389249	39	0	0
T5	2687	0	0	0
T6	5834	0	0	0
T7	2916	10	0	0
T8	5407	1	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T31	0	12	0	0
T32	0	8	0	0
T93	0	21	0	0
T96	0	12	0	0
T97	0	11	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	14981	0	0
T1	7474	9	0	0
T2	11022	9	0	0
T3	5830	0	0	0
T4	389249	348	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	10	0	0
T8	5407	5	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1260	0	0
T1	7474	9	0	0
T2	11022	9	0	0
T3	5830	0	0	0
T4	389249	39	0	0
T5	2687	0	0	0
T6	5834	0	0	0
T7	2916	10	0	0
T8	5407	1	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T31	0	12	0	0
T32	0	8	0	0
T93	0	21	0	0
T96	0	12	0	0
T97	0	11	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	15004	0	0
T1	7474	9	0	0
T2	11022	10	0	0
T3	5830	0	0	0
T4	389249	344	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	8	0	0
T8	5407	5	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1283	0	0
T1	7474	9	0	0
T2	11022	10	0	0
T3	5830	0	0	0
T4	389249	36	0	0
T5	2687	0	0	0
T6	5834	0	0	0
T7	2916	8	0	0
T8	5407	1	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T14	0	1	0	0
T31	0	12	0	0
T32	0	9	0	0
T93	0	21	0	0
T96	0	12	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	15004	0	0
T1	7474	9	0	0
T2	11022	10	0	0
T3	5830	0	0	0
T4	389249	344	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	8	0	0
T8	5407	5	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1283	0	0
T1	7474	9	0	0
T2	11022	10	0	0
T3	5830	0	0	0
T4	389249	36	0	0
T5	2687	0	0	0
T6	5834	0	0	0
T7	2916	8	0	0
T8	5407	1	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T14	0	1	0	0
T31	0	12	0	0
T32	0	9	0	0
T93	0	21	0	0
T96	0	12	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	15028	0	0
T1	7474	11	0	0
T2	11022	11	0	0
T3	5830	0	0	0
T4	389249	346	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	12	0	0
T8	5407	5	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1298	0	0
T1	7474	11	0	0
T2	11022	11	0	0
T3	5830	0	0	0
T4	389249	38	0	0
T5	2687	0	0	0
T6	5834	0	0	0
T7	2916	12	0	0
T8	5407	1	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T31	0	14	0	0
T32	0	11	0	0
T93	0	16	0	0
T96	0	11	0	0
T97	0	12	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	15028	0	0
T1	7474	11	0	0
T2	11022	11	0	0
T3	5830	0	0	0
T4	389249	346	0	0
T5	2687	9	0	0
T6	5834	0	0	0
T7	2916	12	0	0
T8	5407	5	0	0
T9	1994	0	0	0
T10	34750	31	0	0
T11	0	20	0	0
T12	0	39	0	0
T13	0	75	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13111695	1298	0	0
T1	7474	11	0	0
T2	11022	11	0	0
T3	5830	0	0	0
T4	389249	38	0	0
T5	2687	0	0	0
T6	5834	0	0	0
T7	2916	12	0	0
T8	5407	1	0	0
T9	1994	0	0	0
T10	34750	0	0	0
T31	0	14	0	0
T32	0	11	0	0
T93	0	16	0	0
T96	0	11	0	0
T97	0	12	0	0