Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12323549	6864	0	0
alert_regwen_rd_A	12323549	5347	0	0
cpu_regwen_rd_A	12323549	5084	0	0
sw_rst_ctrl_n_0_rd_A	12323549	10227	0	0
sw_rst_ctrl_n_1_rd_A	12323549	10504	0	0
sw_rst_ctrl_n_2_rd_A	12323549	10356	0	0
sw_rst_ctrl_n_3_rd_A	12323549	10462	0	0
sw_rst_ctrl_n_4_rd_A	12323549	10573	0	0
sw_rst_ctrl_n_5_rd_A	12323549	10334	0	0
sw_rst_ctrl_n_6_rd_A	12323549	10539	0	0
sw_rst_ctrl_n_7_rd_A	12323549	10195	0	0
sw_rst_regwen_0_rd_A	12323549	5720	0	0
sw_rst_regwen_1_rd_A	12323549	5721	0	0
sw_rst_regwen_2_rd_A	12323549	5785	0	0
sw_rst_regwen_3_rd_A	12323549	5816	0	0
sw_rst_regwen_4_rd_A	12323549	5672	0	0
sw_rst_regwen_5_rd_A	12323549	5776	0	0
sw_rst_regwen_6_rd_A	12323549	5713	0	0
sw_rst_regwen_7_rd_A	12323549	5579	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	6864	0	0
T73	21349	3	0	0
T74	4530	80	0	0
T75	2825	17	0	0
T76	2368	121	0	0
T77	17885	3	0	0
T81	2893	10	0	0
T98	4211	287	0	0
T99	10623	2	0	0
T100	9473	299	0	0
T101	2596	64	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5347	0	0
T4	349616	552	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	0	0	0
T9	1904	0	0	0
T10	30760	55	0	0
T11	2621	0	0	0
T12	27234	0	0	0
T17	1628	0	0	0
T64	0	37	0	0
T109	0	152	0	0
T111	0	356	0	0
T113	0	34	0	0
T130	0	19	0	0
T131	0	312	0	0
T132	0	214	0	0
T133	0	75	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5084	0	0
T4	349616	534	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	0	0	0
T9	1904	0	0	0
T10	30760	56	0	0
T11	2621	0	0	0
T12	27234	0	0	0
T17	1628	0	0	0
T64	0	43	0	0
T109	0	111	0	0
T111	0	323	0	0
T113	0	34	0	0
T130	0	32	0	0
T131	0	299	0	0
T132	0	213	0	0
T133	0	88	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10227	0	0
T2	10980	160	0	0
T3	5674	0	0	0
T4	349616	1018	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	2	0	0
T9	1904	0	0	0
T10	30760	43	0	0
T11	2621	0	0	0
T14	0	16	0	0
T47	0	2	0	0
T58	0	216	0	0
T64	0	47	0	0
T97	0	192	0	0
T134	0	150	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10504	0	0
T2	10980	174	0	0
T3	5674	0	0	0
T4	349616	930	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	8	0	0
T9	1904	0	0	0
T10	30760	51	0	0
T11	2621	0	0	0
T14	0	11	0	0
T47	0	4	0	0
T58	0	216	0	0
T64	0	25	0	0
T97	0	202	0	0
T134	0	102	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10356	0	0
T2	10980	157	0	0
T3	5674	0	0	0
T4	349616	1043	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	10	0	0
T9	1904	0	0	0
T10	30760	44	0	0
T11	2621	0	0	0
T14	0	8	0	0
T47	0	9	0	0
T58	0	220	0	0
T64	0	45	0	0
T97	0	226	0	0
T134	0	127	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10462	0	0
T2	10980	145	0	0
T3	5674	0	0	0
T4	349616	1072	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	4	0	0
T9	1904	0	0	0
T10	30760	60	0	0
T11	2621	0	0	0
T14	0	10	0	0
T47	0	15	0	0
T58	0	241	0	0
T64	0	43	0	0
T97	0	211	0	0
T134	0	131	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10573	0	0
T2	10980	179	0	0
T3	5674	0	0	0
T4	349616	1017	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	7	0	0
T9	1904	0	0	0
T10	30760	52	0	0
T11	2621	0	0	0
T14	0	15	0	0
T47	0	5	0	0
T58	0	253	0	0
T64	0	33	0	0
T97	0	184	0	0
T134	0	153	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10334	0	0
T2	10980	159	0	0
T3	5674	0	0	0
T4	349616	1036	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	6	0	0
T9	1904	0	0	0
T10	30760	45	0	0
T11	2621	0	0	0
T14	0	20	0	0
T47	0	17	0	0
T58	0	202	0	0
T64	0	40	0	0
T97	0	178	0	0
T134	0	158	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10539	0	0
T2	10980	198	0	0
T3	5674	0	0	0
T4	349616	984	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	2	0	0
T9	1904	0	0	0
T10	30760	52	0	0
T11	2621	0	0	0
T14	0	17	0	0
T47	0	6	0	0
T58	0	227	0	0
T64	0	44	0	0
T97	0	217	0	0
T134	0	149	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	10195	0	0
T2	10980	172	0	0
T3	5674	0	0	0
T4	349616	938	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	14	0	0
T9	1904	0	0	0
T10	30760	42	0	0
T11	2621	0	0	0
T14	0	7	0	0
T47	0	8	0	0
T58	0	207	0	0
T64	0	46	0	0
T97	0	174	0	0
T134	0	140	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5720	0	0
T2	10980	38	0	0
T3	5674	0	0	0
T4	349616	494	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	0	0	0
T9	1904	0	0	0
T10	30760	54	0	0
T11	2621	0	0	0
T14	0	4	0	0
T58	0	43	0	0
T64	0	32	0	0
T97	0	32	0	0
T109	0	150	0	0
T134	0	34	0	0
T135	0	7	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5721	0	0
T2	10980	21	0	0
T3	5674	0	0	0
T4	349616	508	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	2	0	0
T9	1904	0	0	0
T10	30760	45	0	0
T11	2621	0	0	0
T14	0	7	0	0
T58	0	34	0	0
T64	0	62	0	0
T97	0	35	0	0
T134	0	46	0	0
T135	0	14	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5785	0	0
T2	10980	32	0	0
T3	5674	0	0	0
T4	349616	461	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	5	0	0
T9	1904	0	0	0
T10	30760	46	0	0
T11	2621	0	0	0
T14	0	10	0	0
T58	0	43	0	0
T64	0	42	0	0
T97	0	24	0	0
T134	0	26	0	0
T135	0	6	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5816	0	0
T2	10980	32	0	0
T3	5674	0	0	0
T4	349616	547	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	8	0	0
T9	1904	0	0	0
T10	30760	41	0	0
T11	2621	0	0	0
T14	0	8	0	0
T58	0	27	0	0
T64	0	25	0	0
T97	0	33	0	0
T134	0	23	0	0
T135	0	7	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5672	0	0
T2	10980	38	0	0
T3	5674	0	0	0
T4	349616	531	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	0	0	0
T9	1904	0	0	0
T10	30760	39	0	0
T11	2621	0	0	0
T14	0	9	0	0
T58	0	48	0	0
T64	0	20	0	0
T97	0	34	0	0
T109	0	145	0	0
T134	0	37	0	0
T135	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5776	0	0
T2	10980	34	0	0
T3	5674	0	0	0
T4	349616	561	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	2	0	0
T9	1904	0	0	0
T10	30760	38	0	0
T11	2621	0	0	0
T14	0	11	0	0
T58	0	40	0	0
T64	0	44	0	0
T97	0	34	0	0
T134	0	34	0	0
T135	0	9	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5713	0	0
T2	10980	28	0	0
T3	5674	0	0	0
T4	349616	504	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	4	0	0
T9	1904	0	0	0
T10	30760	62	0	0
T11	2621	0	0	0
T14	0	7	0	0
T58	0	23	0	0
T64	0	40	0	0
T97	0	25	0	0
T134	0	28	0	0
T135	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12323549	5579	0	0
T2	10980	27	0	0
T3	5674	0	0	0
T4	349616	513	0	0
T5	2094	0	0	0
T6	5096	0	0	0
T7	2827	0	0	0
T8	5021	3	0	0
T9	1904	0	0	0
T10	30760	39	0	0
T11	2621	0	0	0
T14	0	15	0	0
T58	0	30	0	0
T64	0	40	0	0
T97	0	35	0	0
T134	0	29	0	0
T135	0	7	0	0