Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605455	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

361811

1

T1

8

T2

100

T3

141

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515360	1			T2	127		T3	186		T4	186
values[0x0]	226152	1			T1	16		T2	69		T3	92
values[0x1]	225754	1			T1	10		T2	62		T3	101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	508391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

458875

1

T1

11

T2

126

T3

176

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4677	1			T5	5		T6	54		T8	14
valid_sources[0x01]	3562	1			T5	2		T6	29		T8	10
valid_sources[0x02]	6599	1			T2	3		T4	2		T5	2
valid_sources[0x03]	7377	1			T5	1		T6	35		T8	10
valid_sources[0x04]	3654	1			T5	2		T6	47		T8	35
valid_sources[0x05]	3551	1			T2	3		T4	1		T5	5
valid_sources[0x06]	3139	1			T5	4		T6	66		T8	32
valid_sources[0x07]	3897	1			T2	4		T5	5		T6	68
valid_sources[0x08]	3280	1			T5	2		T6	37		T8	18
valid_sources[0x09]	3274	1			T2	1		T6	28		T8	20
valid_sources[0x0a]	4575	1			T5	5		T6	50		T8	15
valid_sources[0x0b]	5175	1			T4	1		T5	3		T6	52
valid_sources[0x0c]	3121	1			T5	4		T6	56		T8	7
valid_sources[0x0d]	3589	1			T5	4		T6	60		T8	19
valid_sources[0x0e]	3366	1			T5	1		T6	88		T8	2
valid_sources[0x0f]	6628	1			T4	2		T5	2		T6	54
valid_sources[0x10]	3144	1			T5	6		T6	62		T8	24
valid_sources[0x11]	3172	1			T5	4		T6	42		T8	23
valid_sources[0x12]	3375	1			T5	8		T6	77		T8	12
valid_sources[0x13]	3145	1			T4	3		T5	3		T6	51
valid_sources[0x14]	4244	1			T2	1		T5	7		T6	74
valid_sources[0x15]	2948	1			T5	3		T6	34		T8	6
valid_sources[0x16]	3339	1			T2	2		T5	3		T6	40
valid_sources[0x17]	3767	1			T2	1		T4	1		T5	3
valid_sources[0x18]	3890	1			T5	4		T6	57		T8	25
valid_sources[0x19]	3658	1			T2	8		T5	9		T6	44
valid_sources[0x1a]	6656	1			T2	2		T5	9		T6	51
valid_sources[0x1b]	3276	1			T2	3		T4	3		T5	4
valid_sources[0x1c]	2927	1			T2	1		T5	5		T6	54
valid_sources[0x1d]	3967	1			T5	4		T6	49		T8	9
valid_sources[0x1e]	3113	1			T5	1		T6	32		T8	11
valid_sources[0x1f]	3321	1			T5	4		T6	41		T8	3
valid_sources[0x20]	3708	1			T2	6		T4	1		T5	3
valid_sources[0x21]	4274	1			T5	7		T6	54		T8	21
valid_sources[0x22]	6963	1			T4	4		T5	4		T6	35
valid_sources[0x23]	3722	1			T5	3		T6	61		T8	10
valid_sources[0x24]	4880	1			T5	1		T6	58		T8	14
valid_sources[0x25]	3275	1			T4	1		T5	5		T6	57
valid_sources[0x26]	3063	1			T2	1		T5	1		T6	89
valid_sources[0x27]	3121	1			T2	10		T4	3		T5	5
valid_sources[0x28]	3028	1			T2	6		T4	3		T5	6
valid_sources[0x29]	3242	1			T5	6		T6	68		T8	6
valid_sources[0x2a]	3338	1			T4	2		T5	1		T6	49
valid_sources[0x2b]	4318	1			T4	4		T6	47		T8	15
valid_sources[0x2c]	3391	1			T4	1		T5	3		T6	43
valid_sources[0x2d]	3081	1			T2	2		T5	3		T6	51
valid_sources[0x2e]	3075	1			T4	5		T5	9		T6	35
valid_sources[0x2f]	3821	1			T5	5		T6	72		T8	10
valid_sources[0x30]	3628	1			T4	2		T5	3		T6	51
valid_sources[0x31]	3671	1			T5	6		T6	57		T8	7
valid_sources[0x32]	3090	1			T2	2		T4	5		T5	3
valid_sources[0x33]	3535	1			T5	3		T6	75		T8	10
valid_sources[0x34]	3636	1			T2	6		T4	9		T5	2
valid_sources[0x35]	3309	1			T5	3		T6	81		T8	8
valid_sources[0x36]	3650	1			T4	2		T5	2		T6	62
valid_sources[0x37]	3276	1			T2	7		T4	6		T5	6
valid_sources[0x38]	3648	1			T2	1		T4	2		T5	3
valid_sources[0x39]	6662	1			T4	1		T5	2		T6	53
valid_sources[0x3a]	5570	1			T5	9		T6	53		T8	21
valid_sources[0x3b]	3737	1			T4	1		T5	5		T6	45
valid_sources[0x3c]	3315	1			T2	4		T4	2		T5	2
valid_sources[0x3d]	4355	1			T2	3		T4	2		T5	6
valid_sources[0x3e]	3738	1			T4	2		T5	2		T6	50
valid_sources[0x3f]	3329	1			T5	7		T6	47		T8	18
valid_sources[0x40]	3088	1			T5	6		T6	62		T8	15
valid_sources[0x41]	3184	1			T5	6		T6	49		T8	6
valid_sources[0x42]	3624	1			T4	4		T5	7		T6	66
valid_sources[0x43]	3918	1			T4	2		T5	5		T6	46
valid_sources[0x44]	3059	1			T4	13		T5	3		T6	84
valid_sources[0x45]	3668	1			T4	7		T5	2		T6	55
valid_sources[0x46]	3601	1			T5	4		T6	64		T8	7
valid_sources[0x47]	3469	1			T5	2		T6	24		T8	7
valid_sources[0x48]	3438	1			T5	3		T6	69		T8	12
valid_sources[0x49]	3550	1			T5	7		T6	63		T8	9
valid_sources[0x4a]	4468	1			T5	4		T6	48		T8	24
valid_sources[0x4b]	3466	1			T2	7		T6	49		T8	41
valid_sources[0x4c]	4528	1			T4	2		T5	5		T6	54
valid_sources[0x4d]	3614	1			T5	3		T6	48		T8	6
valid_sources[0x4e]	3129	1			T4	3		T5	1		T6	82
valid_sources[0x4f]	3727	1			T5	1		T6	34		T8	12
valid_sources[0x50]	3303	1			T4	2		T5	5		T6	74
valid_sources[0x51]	3727	1			T2	1		T4	2		T5	4
valid_sources[0x52]	2998	1			T4	2		T5	1		T6	53
valid_sources[0x53]	3700	1			T2	6		T4	1		T5	4
valid_sources[0x54]	2734	1			T2	4		T5	4		T6	89
valid_sources[0x55]	2966	1			T6	26		T8	12		T9	7
valid_sources[0x56]	3772	1			T2	1		T4	2		T5	3
valid_sources[0x57]	3478	1			T4	1		T5	9		T6	42
valid_sources[0x58]	3131	1			T4	2		T5	6		T6	57
valid_sources[0x59]	6339	1			T4	2		T5	1		T6	44
valid_sources[0x5a]	3852	1			T4	8		T5	3		T6	64
valid_sources[0x5b]	3585	1			T2	4		T6	56		T8	9
valid_sources[0x5c]	5065	1			T2	6		T4	1		T5	3
valid_sources[0x5d]	3707	1			T2	1		T4	1		T5	2
valid_sources[0x5e]	3973	1			T2	1		T5	5		T6	48
valid_sources[0x5f]	3931	1			T5	2		T6	35		T8	17
valid_sources[0x60]	3464	1			T5	2		T6	62		T8	8
valid_sources[0x61]	3355	1			T4	4		T5	8		T6	52
valid_sources[0x62]	3382	1			T2	3		T5	5		T6	69
valid_sources[0x63]	3036	1			T2	2		T4	1		T5	2
valid_sources[0x64]	4225	1			T5	3		T6	63		T8	6
valid_sources[0x65]	2968	1			T2	5		T5	5		T6	39
valid_sources[0x66]	4308	1			T2	2		T4	2		T5	2
valid_sources[0x67]	2819	1			T4	4		T5	9		T6	36
valid_sources[0x68]	3618	1			T2	2		T5	4		T6	53
valid_sources[0x69]	3290	1			T2	1		T4	1		T5	2
valid_sources[0x6a]	3322	1			T2	4		T4	1		T5	4
valid_sources[0x6b]	3955	1			T4	1		T5	3		T6	31
valid_sources[0x6c]	5611	1			T5	3		T6	61		T8	18
valid_sources[0x6d]	3898	1			T6	90		T8	3		T9	21
valid_sources[0x6e]	4715	1			T5	7		T6	50		T8	26
valid_sources[0x6f]	3341	1			T5	1		T6	61		T8	37
valid_sources[0x70]	3106	1			T2	2		T5	13		T6	67
valid_sources[0x71]	3805	1			T2	1		T4	1		T5	6
valid_sources[0x72]	4204	1			T4	5		T5	4		T6	72
valid_sources[0x73]	3830	1			T2	2		T5	2		T6	53
valid_sources[0x74]	3698	1			T4	4		T5	7		T6	69
valid_sources[0x75]	3675	1			T4	1		T5	4		T6	43
valid_sources[0x76]	3554	1			T2	1		T4	1		T5	8
valid_sources[0x77]	3452	1			T2	6		T4	2		T5	7
valid_sources[0x78]	3858	1			T2	5		T4	2		T5	8
valid_sources[0x79]	3537	1			T2	2		T5	5		T6	34
valid_sources[0x7a]	3377	1			T5	9		T6	45		T8	16
valid_sources[0x7b]	3693	1			T2	1		T4	8		T5	2
valid_sources[0x7c]	3676	1			T5	3		T6	51		T8	9
valid_sources[0x7d]	5597	1			T2	7		T5	4		T6	81
valid_sources[0x7e]	3324	1			T5	2		T6	39		T8	15
valid_sources[0x7f]	3827	1			T4	4		T5	5		T6	63
valid_sources[0x80]	3419	1			T4	2		T5	4		T6	82

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241442

1

T2

65

T3

98

T4

88

values[0x0]

all_enables

biggest_size

78479

1

T1

5

T2

22

T3

26

values[0x1]

all_enables

biggest_size

41890

1

T1

3

T2

13

T3

17