Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T3,T4,T6

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11728114	12965	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11728114	119666	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11728114	6999732	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11728114	190586	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11728114	12965	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11728114	119666	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11728114	6999732	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11728114	190586	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	12965	0	0
T2	4403	14	0	0
T3	2443	4	0	0
T4	4219	4	0	0
T5	8549	0	0	0
T6	80596	159	0	0
T7	25958	75	0	0
T8	53644	75	0	0
T9	53264	75	0	0
T10	2297	4	0	0
T11	18372	42	0	0
T12	0	16	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	119666	0	0
T2	4403	126	0	0
T3	2443	37	0	0
T4	4219	37	0	0
T5	8549	0	0	0
T6	80596	1440	0	0
T7	25958	703	0	0
T8	53644	717	0	0
T9	53264	723	0	0
T10	2297	38	0	0
T11	18372	378	0	0
T12	0	144	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	6999732	0	0
T1	1793	1151	0	0
T2	4403	3585	0	0
T3	2443	1499	0	0
T4	4219	3286	0	0
T5	8549	7956	0	0
T6	80596	45923	0	0
T7	25958	8730	0	0
T8	53644	36143	0	0
T9	53264	35636	0	0
T10	2297	1318	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	190586	0	0
T2	4403	197	0	0
T3	2443	60	0	0
T4	4219	57	0	0
T5	8549	0	0	0
T6	80596	2304	0	0
T7	25958	1099	0	0
T8	53644	1124	0	0
T9	53264	1198	0	0
T10	2297	57	0	0
T11	18372	626	0	0
T12	0	220	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	12965	0	0
T2	4403	14	0	0
T3	2443	4	0	0
T4	4219	4	0	0
T5	8549	0	0	0
T6	80596	159	0	0
T7	25958	75	0	0
T8	53644	75	0	0
T9	53264	75	0	0
T10	2297	4	0	0
T11	18372	42	0	0
T12	0	16	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	119666	0	0
T2	4403	126	0	0
T3	2443	37	0	0
T4	4219	37	0	0
T5	8549	0	0	0
T6	80596	1440	0	0
T7	25958	703	0	0
T8	53644	717	0	0
T9	53264	723	0	0
T10	2297	38	0	0
T11	18372	378	0	0
T12	0	144	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	6999732	0	0
T1	1793	1151	0	0
T2	4403	3585	0	0
T3	2443	1499	0	0
T4	4219	3286	0	0
T5	8549	7956	0	0
T6	80596	45923	0	0
T7	25958	8730	0	0
T8	53644	36143	0	0
T9	53264	35636	0	0
T10	2297	1318	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	190586	0	0
T2	4403	197	0	0
T3	2443	60	0	0
T4	4219	57	0	0
T5	8549	0	0	0
T6	80596	2304	0	0
T7	25958	1099	0	0
T8	53644	1124	0	0
T9	53264	1198	0	0
T10	2297	57	0	0
T11	18372	626	0	0
T12	0	220	0	0