Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T6,T11,T48
1	0	Covered	T3,T4,T6

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54908155	8708	0	0
CascadeEffAonToRstPorAboveRise_A	54908155	8708	0	0
CascadeEffAonToRstPorIoAboveFall_A	52709657	8708	0	0
CascadeEffAonToRstPorIoAboveRise_A	52709657	8708	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26355577	8708	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26355577	8708	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13177616	8708	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13177616	8708	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26355842	8708	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26355842	8708	0	0
CascadeLcToLcAboveFall_A	54908155	21673	0	0
CascadeLcToLcAboveRise_A	54908155	21673	0	0
CascadeLcToLcAonAboveFall_A	1664034	21673	0	0
CascadeLcToLcAonAboveRise_A	1664034	21673	0	0
CascadeLcToLcShadowedAboveFall_A	54908155	21673	0	0
CascadeLcToLcShadowedAboveRise_A	54908155	21673	0	0
CascadePorToAonAboveFall_A	1664034	6931	0	0
CascadeSysToSysAboveFall_A	54908155	21673	0	0
CascadeSysToSysAboveRise_A	54908155	21673	0	0
ScanRstToAonRise_A	1664034	186	0	0
StablePorToAonRise_A	1664034	8708	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11728114	21673	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11728114	21673	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11728114	21673	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11728114	21673	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13177616	21673	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13177616	21673	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11728114	21673	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11728114	21673	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11728114	21673	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11728114	21673	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	8708	0	0
T1	7551	1	0	0
T2	21830	1	0	0
T3	11794	2	0	0
T4	18795	2	0	0
T5	35901	1	0	0
T6	420602	79	0	0
T7	122701	27	0	0
T8	236033	27	0	0
T9	234549	27	0	0
T10	10569	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	8708	0	0
T1	7551	1	0	0
T2	21830	1	0	0
T3	11794	2	0	0
T4	18795	2	0	0
T5	35901	1	0	0
T6	420602	79	0	0
T7	122701	27	0	0
T8	236033	27	0	0
T9	234549	27	0	0
T10	10569	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52709657	8708	0	0
T1	7248	1	0	0
T2	20956	1	0	0
T3	11319	2	0	0
T4	18047	2	0	0
T5	34463	1	0	0
T6	403813	79	0	0
T7	117827	27	0	0
T8	226583	27	0	0
T9	225165	27	0	0
T10	10149	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52709657	8708	0	0
T1	7248	1	0	0
T2	20956	1	0	0
T3	11319	2	0	0
T4	18047	2	0	0
T5	34463	1	0	0
T6	403813	79	0	0
T7	117827	27	0	0
T8	226583	27	0	0
T9	225165	27	0	0
T10	10149	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355577	8708	0	0
T1	3624	1	0	0
T2	10477	1	0	0
T3	5662	2	0	0
T4	9022	2	0	0
T5	17232	1	0	0
T6	201902	79	0	0
T7	58891	27	0	0
T8	113280	27	0	0
T9	112578	27	0	0
T10	5073	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355577	8708	0	0
T1	3624	1	0	0
T2	10477	1	0	0
T3	5662	2	0	0
T4	9022	2	0	0
T5	17232	1	0	0
T6	201902	79	0	0
T7	58891	27	0	0
T8	113280	27	0	0
T9	112578	27	0	0
T10	5073	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	8708	0	0
T1	1811	1	0	0
T2	5238	1	0	0
T3	2832	2	0	0
T4	4510	2	0	0
T5	8615	1	0	0
T6	100962	79	0	0
T7	29450	27	0	0
T8	56662	27	0	0
T9	56299	27	0	0
T10	2535	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	8708	0	0
T1	1811	1	0	0
T2	5238	1	0	0
T3	2832	2	0	0
T4	4510	2	0	0
T5	8615	1	0	0
T6	100962	79	0	0
T7	29450	27	0	0
T8	56662	27	0	0
T9	56299	27	0	0
T10	2535	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355842	8708	0	0
T1	3624	1	0	0
T2	10478	1	0	0
T3	5660	2	0	0
T4	9024	2	0	0
T5	17231	1	0	0
T6	201918	79	0	0
T7	58905	27	0	0
T8	113295	27	0	0
T9	112576	27	0	0
T10	5075	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355842	8708	0	0
T1	3624	1	0	0
T2	10478	1	0	0
T3	5660	2	0	0
T4	9024	2	0	0
T5	17231	1	0	0
T6	201918	79	0	0
T7	58905	27	0	0
T8	113295	27	0	0
T9	112576	27	0	0
T10	5075	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	21673	0	0
T1	7551	1	0	0
T2	21830	15	0	0
T3	11794	6	0	0
T4	18795	6	0	0
T5	35901	1	0	0
T6	420602	238	0	0
T7	122701	102	0	0
T8	236033	102	0	0
T9	234549	102	0	0
T10	10569	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	21673	0	0
T1	7551	1	0	0
T2	21830	15	0	0
T3	11794	6	0	0
T4	18795	6	0	0
T5	35901	1	0	0
T6	420602	238	0	0
T7	122701	102	0	0
T8	236033	102	0	0
T9	234549	102	0	0
T10	10569	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	21673	0	0
T1	225	1	0	0
T2	653	15	0	0
T3	352	6	0	0
T4	563	6	0	0
T5	1076	1	0	0
T6	12923	238	0	0
T7	3697	102	0	0
T8	7095	102	0	0
T9	7050	102	0	0
T10	316	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	21673	0	0
T1	225	1	0	0
T2	653	15	0	0
T3	352	6	0	0
T4	563	6	0	0
T5	1076	1	0	0
T6	12923	238	0	0
T7	3697	102	0	0
T8	7095	102	0	0
T9	7050	102	0	0
T10	316	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	21673	0	0
T1	7551	1	0	0
T2	21830	15	0	0
T3	11794	6	0	0
T4	18795	6	0	0
T5	35901	1	0	0
T6	420602	238	0	0
T7	122701	102	0	0
T8	236033	102	0	0
T9	234549	102	0	0
T10	10569	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	21673	0	0
T1	7551	1	0	0
T2	21830	15	0	0
T3	11794	6	0	0
T4	18795	6	0	0
T5	35901	1	0	0
T6	420602	238	0	0
T7	122701	102	0	0
T8	236033	102	0	0
T9	234549	102	0	0
T10	10569	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	6931	0	0
T1	225	1	0	0
T2	653	1	0	0
T3	352	1	0	0
T4	563	1	0	0
T5	1076	1	0	0
T6	12923	35	0	0
T7	3697	27	0	0
T8	7095	27	0	0
T9	7050	27	0	0
T10	316	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	21673	0	0
T1	7551	1	0	0
T2	21830	15	0	0
T3	11794	6	0	0
T4	18795	6	0	0
T5	35901	1	0	0
T6	420602	238	0	0
T7	122701	102	0	0
T8	236033	102	0	0
T9	234549	102	0	0
T10	10569	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54908155	21673	0	0
T1	7551	1	0	0
T2	21830	15	0	0
T3	11794	6	0	0
T4	18795	6	0	0
T5	35901	1	0	0
T6	420602	238	0	0
T7	122701	102	0	0
T8	236033	102	0	0
T9	234549	102	0	0
T10	10569	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	186	0	0
T6	12923	3	0	0
T7	3697	0	0	0
T8	7095	0	0	0
T9	7050	0	0	0
T10	316	0	0	0
T11	3107	3	0	0
T12	645	0	0	0
T23	0	5	0	0
T28	0	2	0	0
T30	0	1	0	0
T41	347	0	0	0
T42	730	0	0	0
T43	737	0	0	0
T87	0	2	0	0
T88	0	3	0	0
T97	0	2	0	0
T99	0	1	0	0
T106	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	8708	0	0
T1	225	1	0	0
T2	653	1	0	0
T3	352	2	0	0
T4	563	2	0	0
T5	1076	1	0	0
T6	12923	79	0	0
T7	3697	27	0	0
T8	7095	27	0	0
T9	7050	27	0	0
T10	316	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	21673	0	0
T1	1811	1	0	0
T2	5238	15	0	0
T3	2832	6	0	0
T4	4510	6	0	0
T5	8615	1	0	0
T6	100962	238	0	0
T7	29450	102	0	0
T8	56662	102	0	0
T9	56299	102	0	0
T10	2535	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	21673	0	0
T1	1811	1	0	0
T2	5238	15	0	0
T3	2832	6	0	0
T4	4510	6	0	0
T5	8615	1	0	0
T6	100962	238	0	0
T7	29450	102	0	0
T8	56662	102	0	0
T9	56299	102	0	0
T10	2535	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11728114	21673	0	0
T1	1793	1	0	0
T2	4403	15	0	0
T3	2443	6	0	0
T4	4219	6	0	0
T5	8549	1	0	0
T6	80596	238	0	0
T7	25958	102	0	0
T8	53644	102	0	0
T9	53264	102	0	0
T10	2297	6	0	0