Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T41
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T23
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T23
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T6
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13177616	13845	0	0
gen_assertions[0].RstEnOn_A	13177616	1035	0	0
gen_assertions[0].RstNOff_A	13177616	13845	0	0
gen_assertions[0].RstNOn_A	13177616	1035	0	0
gen_assertions[1].RstEnOff_A	52709657	12549	0	0
gen_assertions[1].RstEnOn_A	52709657	987	0	0
gen_assertions[1].RstNOff_A	52709657	12549	0	0
gen_assertions[1].RstNOn_A	52709657	987	0	0
gen_assertions[2].RstEnOff_A	26355577	12619	0	0
gen_assertions[2].RstEnOn_A	26355577	1013	0	0
gen_assertions[2].RstNOff_A	26355577	12619	0	0
gen_assertions[2].RstNOn_A	26355577	1013	0	0
gen_assertions[3].RstEnOff_A	26355842	12653	0	0
gen_assertions[3].RstEnOn_A	26355842	1046	0	0
gen_assertions[3].RstNOff_A	26355842	12653	0	0
gen_assertions[3].RstNOn_A	26355842	1046	0	0
gen_assertions[4].RstEnOff_A	1664034	21496	0	0
gen_assertions[4].RstEnOn_A	1664034	1104	0	0
gen_assertions[4].RstNOff_A	1664034	21496	0	0
gen_assertions[4].RstNOn_A	1664034	1104	0	0
gen_assertions[5].RstEnOff_A	13177616	14076	0	0
gen_assertions[5].RstEnOn_A	13177616	1146	0	0
gen_assertions[5].RstNOff_A	13177616	14076	0	0
gen_assertions[5].RstNOn_A	13177616	1146	0	0
gen_assertions[6].RstEnOff_A	13177616	14132	0	0
gen_assertions[6].RstEnOn_A	13177616	1202	0	0
gen_assertions[6].RstNOff_A	13177616	14132	0	0
gen_assertions[6].RstNOn_A	13177616	1202	0	0
gen_assertions[7].RstEnOff_A	13177616	14158	0	0
gen_assertions[7].RstEnOn_A	13177616	1226	0	0
gen_assertions[7].RstNOff_A	13177616	14158	0	0
gen_assertions[7].RstNOn_A	13177616	1226	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	13845	0	0
T2	5238	14	0	0
T3	2832	5	0	0
T4	4510	4	0	0
T5	8615	4	0	0
T6	100962	186	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1035	0	0
T2	5238	2	0	0
T3	2832	1	0	0
T4	4510	0	0	0
T5	8615	4	0	0
T6	100962	29	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	0	2	0	0
T23	0	6	0	0
T27	0	1	0	0
T41	0	8	0	0
T43	0	2	0	0
T83	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	13845	0	0
T2	5238	14	0	0
T3	2832	5	0	0
T4	4510	4	0	0
T5	8615	4	0	0
T6	100962	186	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1035	0	0
T2	5238	2	0	0
T3	2832	1	0	0
T4	4510	0	0	0
T5	8615	4	0	0
T6	100962	29	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	0	2	0	0
T23	0	6	0	0
T27	0	1	0	0
T41	0	8	0	0
T43	0	2	0	0
T83	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52709657	12549	0	0
T2	20956	13	0	0
T3	11319	5	0	0
T4	18047	2	0	0
T5	34463	7	0	0
T6	403813	180	0	0
T7	117827	68	0	0
T8	226583	58	0	0
T9	225165	72	0	0
T10	10149	4	0	0
T11	97760	38	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52709657	987	0	0
T3	11319	1	0	0
T4	18047	0	0	0
T5	34463	7	0	0
T6	403813	38	0	0
T7	117827	0	0	0
T8	226583	0	0	0
T9	225165	0	0	0
T10	10149	0	0	0
T11	97760	0	0	0
T12	20666	0	0	0
T23	0	4	0	0
T24	0	1	0	0
T27	0	1	0	0
T41	0	4	0	0
T59	0	5	0	0
T83	0	2	0	0
T84	0	2	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52709657	12549	0	0
T2	20956	13	0	0
T3	11319	5	0	0
T4	18047	2	0	0
T5	34463	7	0	0
T6	403813	180	0	0
T7	117827	68	0	0
T8	226583	58	0	0
T9	225165	72	0	0
T10	10149	4	0	0
T11	97760	38	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52709657	987	0	0
T3	11319	1	0	0
T4	18047	0	0	0
T5	34463	7	0	0
T6	403813	38	0	0
T7	117827	0	0	0
T8	226583	0	0	0
T9	225165	0	0	0
T10	10149	0	0	0
T11	97760	0	0	0
T12	20666	0	0	0
T23	0	4	0	0
T24	0	1	0	0
T27	0	1	0	0
T41	0	4	0	0
T59	0	5	0	0
T83	0	2	0	0
T84	0	2	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355577	12619	0	0
T2	10477	13	0	0
T3	5662	4	0	0
T4	9022	2	0	0
T5	17232	10	0	0
T6	201902	179	0	0
T7	58891	68	0	0
T8	113280	58	0	0
T9	112578	72	0	0
T10	5073	4	0	0
T11	48887	38	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355577	1013	0	0
T5	17232	10	0	0
T6	201902	35	0	0
T7	58891	0	0	0
T8	113280	0	0	0
T9	112578	0	0	0
T10	5073	0	0	0
T11	48887	0	0	0
T12	10332	0	0	0
T23	0	8	0	0
T24	0	1	0	0
T41	5585	1	0	0
T42	11658	0	0	0
T59	0	6	0	0
T60	0	9	0	0
T85	0	15	0	0
T86	0	3	0	0
T87	0	16	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355577	12619	0	0
T2	10477	13	0	0
T3	5662	4	0	0
T4	9022	2	0	0
T5	17232	10	0	0
T6	201902	179	0	0
T7	58891	68	0	0
T8	113280	58	0	0
T9	112578	72	0	0
T10	5073	4	0	0
T11	48887	38	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355577	1013	0	0
T5	17232	10	0	0
T6	201902	35	0	0
T7	58891	0	0	0
T8	113280	0	0	0
T9	112578	0	0	0
T10	5073	0	0	0
T11	48887	0	0	0
T12	10332	0	0	0
T23	0	8	0	0
T24	0	1	0	0
T41	5585	1	0	0
T42	11658	0	0	0
T59	0	6	0	0
T60	0	9	0	0
T85	0	15	0	0
T86	0	3	0	0
T87	0	16	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355842	12653	0	0
T2	10478	13	0	0
T3	5660	4	0	0
T4	9024	3	0	0
T5	17231	7	0	0
T6	201918	176	0	0
T7	58905	68	0	0
T8	113295	58	0	0
T9	112576	72	0	0
T10	5075	4	0	0
T11	48881	38	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355842	1046	0	0
T4	9024	1	0	0
T5	17231	7	0	0
T6	201918	36	0	0
T7	58905	0	0	0
T8	113295	0	0	0
T9	112576	0	0	0
T10	5075	0	0	0
T11	48881	0	0	0
T12	10332	0	0	0
T23	0	5	0	0
T41	5585	0	0	0
T59	0	7	0	0
T60	0	7	0	0
T65	0	1	0	0
T85	0	14	0	0
T86	0	5	0	0
T87	0	13	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355842	12653	0	0
T2	10478	13	0	0
T3	5660	4	0	0
T4	9024	3	0	0
T5	17231	7	0	0
T6	201918	176	0	0
T7	58905	68	0	0
T8	113295	58	0	0
T9	112576	72	0	0
T10	5075	4	0	0
T11	48881	38	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26355842	1046	0	0
T4	9024	1	0	0
T5	17231	7	0	0
T6	201918	36	0	0
T7	58905	0	0	0
T8	113295	0	0	0
T9	112576	0	0	0
T10	5075	0	0	0
T11	48881	0	0	0
T12	10332	0	0	0
T23	0	5	0	0
T41	5585	0	0	0
T59	0	7	0	0
T60	0	7	0	0
T65	0	1	0	0
T85	0	14	0	0
T86	0	5	0	0
T87	0	13	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	21496	0	0
T1	225	1	0	0
T2	653	15	0	0
T3	352	6	0	0
T4	563	6	0	0
T5	1076	12	0	0
T6	12923	269	0	0
T7	3697	76	0	0
T8	7095	94	0	0
T9	7050	96	0	0
T10	316	5	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	1104	0	0
T5	1076	11	0	0
T6	12923	35	0	0
T7	3697	0	0	0
T8	7095	0	0	0
T9	7050	0	0	0
T10	316	0	0	0
T11	3107	0	0	0
T12	645	0	0	0
T23	0	7	0	0
T24	0	1	0	0
T41	347	0	0	0
T42	730	0	0	0
T59	0	8	0	0
T60	0	10	0	0
T85	0	15	0	0
T86	0	6	0	0
T87	0	13	0	0
T88	0	27	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	21496	0	0
T1	225	1	0	0
T2	653	15	0	0
T3	352	6	0	0
T4	563	6	0	0
T5	1076	12	0	0
T6	12923	269	0	0
T7	3697	76	0	0
T8	7095	94	0	0
T9	7050	96	0	0
T10	316	5	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1664034	1104	0	0
T5	1076	11	0	0
T6	12923	35	0	0
T7	3697	0	0	0
T8	7095	0	0	0
T9	7050	0	0	0
T10	316	0	0	0
T11	3107	0	0	0
T12	645	0	0	0
T23	0	7	0	0
T24	0	1	0	0
T41	347	0	0	0
T42	730	0	0	0
T59	0	8	0	0
T60	0	10	0	0
T85	0	15	0	0
T86	0	6	0	0
T87	0	13	0	0
T88	0	27	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	14076	0	0
T2	5238	14	0	0
T3	2832	4	0	0
T4	4510	4	0	0
T5	8615	11	0	0
T6	100962	191	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1146	0	0
T5	8615	11	0	0
T6	100962	34	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	5166	0	0	0
T23	0	6	0	0
T41	2792	0	0	0
T42	5829	0	0	0
T59	0	9	0	0
T60	0	11	0	0
T85	0	12	0	0
T86	0	6	0	0
T87	0	13	0	0
T88	0	27	0	0
T89	0	6	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	14076	0	0
T2	5238	14	0	0
T3	2832	4	0	0
T4	4510	4	0	0
T5	8615	11	0	0
T6	100962	191	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1146	0	0
T5	8615	11	0	0
T6	100962	34	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	5166	0	0	0
T23	0	6	0	0
T41	2792	0	0	0
T42	5829	0	0	0
T59	0	9	0	0
T60	0	11	0	0
T85	0	12	0	0
T86	0	6	0	0
T87	0	13	0	0
T88	0	27	0	0
T89	0	6	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	14132	0	0
T2	5238	14	0	0
T3	2832	5	0	0
T4	4510	4	0	0
T5	8615	13	0	0
T6	100962	199	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1202	0	0
T3	2832	1	0	0
T4	4510	0	0	0
T5	8615	13	0	0
T6	100962	41	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	5166	0	0	0
T23	0	9	0	0
T59	0	10	0	0
T60	0	14	0	0
T85	0	13	0	0
T86	0	7	0	0
T87	0	14	0	0
T88	0	28	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	14132	0	0
T2	5238	14	0	0
T3	2832	5	0	0
T4	4510	4	0	0
T5	8615	13	0	0
T6	100962	199	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1202	0	0
T3	2832	1	0	0
T4	4510	0	0	0
T5	8615	13	0	0
T6	100962	41	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	5166	0	0	0
T23	0	9	0	0
T59	0	10	0	0
T60	0	14	0	0
T85	0	13	0	0
T86	0	7	0	0
T87	0	14	0	0
T88	0	28	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	14158	0	0
T2	5238	14	0	0
T3	2832	4	0	0
T4	4510	5	0	0
T5	8615	12	0	0
T6	100962	190	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1226	0	0
T4	4510	1	0	0
T5	8615	12	0	0
T6	100962	32	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	5166	0	0	0
T23	0	6	0	0
T41	2792	0	0	0
T59	0	12	0	0
T60	0	13	0	0
T85	0	15	0	0
T86	0	8	0	0
T87	0	10	0	0
T88	0	31	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	14158	0	0
T2	5238	14	0	0
T3	2832	4	0	0
T4	4510	5	0	0
T5	8615	12	0	0
T6	100962	190	0	0
T7	29450	75	0	0
T8	56662	75	0	0
T9	56299	75	0	0
T10	2535	4	0	0
T11	24438	42	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13177616	1226	0	0
T4	4510	1	0	0
T5	8615	12	0	0
T6	100962	32	0	0
T7	29450	0	0	0
T8	56662	0	0	0
T9	56299	0	0	0
T10	2535	0	0	0
T11	24438	0	0	0
T12	5166	0	0	0
T23	0	6	0	0
T41	2792	0	0	0
T59	0	12	0	0
T60	0	13	0	0
T85	0	15	0	0
T86	0	8	0	0
T87	0	10	0	0
T88	0	31	0	0