Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12476122	8128	0	0
alert_regwen_rd_A	12476122	5712	0	0
cpu_regwen_rd_A	12476122	5839	0	0
sw_rst_ctrl_n_0_rd_A	12476122	10864	0	0
sw_rst_ctrl_n_1_rd_A	12476122	10852	0	0
sw_rst_ctrl_n_2_rd_A	12476122	10800	0	0
sw_rst_ctrl_n_3_rd_A	12476122	10977	0	0
sw_rst_ctrl_n_4_rd_A	12476122	10958	0	0
sw_rst_ctrl_n_5_rd_A	12476122	11213	0	0
sw_rst_ctrl_n_6_rd_A	12476122	10910	0	0
sw_rst_ctrl_n_7_rd_A	12476122	10495	0	0
sw_rst_regwen_0_rd_A	12476122	6326	0	0
sw_rst_regwen_1_rd_A	12476122	6430	0	0
sw_rst_regwen_2_rd_A	12476122	6348	0	0
sw_rst_regwen_3_rd_A	12476122	6489	0	0
sw_rst_regwen_4_rd_A	12476122	6104	0	0
sw_rst_regwen_5_rd_A	12476122	6241	0	0
sw_rst_regwen_6_rd_A	12476122	6314	0	0
sw_rst_regwen_7_rd_A	12476122	6217	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	8128	0	0
T62	2855	4	0	0
T63	22034	3	0	0
T66	2335	236	0	0
T67	3336	217	0	0
T68	6696	181	0	0
T72	2734	10	0	0
T90	20033	1	0	0
T91	3061	9	0	0
T92	3904	10	0	0
T93	2934	130	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	5712	0	0
T23	188519	203	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	0	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	40	0	0
T31	26169	0	0	0
T89	0	92	0	0
T96	13518	0	0	0
T101	0	204	0	0
T102	0	289	0	0
T104	0	389	0	0
T123	0	55	0	0
T124	0	46	0	0
T125	0	59	0	0
T126	0	123	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	5839	0	0
T23	188519	179	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	0	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	26	0	0
T31	26169	0	0	0
T89	0	87	0	0
T96	13518	0	0	0
T101	0	209	0	0
T102	0	290	0	0
T104	0	504	0	0
T123	0	41	0	0
T124	0	66	0	0
T125	0	73	0	0
T126	0	124	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	10864	0	0
T2	4403	69	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	303	0	0
T27	0	7	0	0
T30	0	32	0	0
T59	0	158	0	0
T89	0	123	0	0
T123	0	69	0	0
T127	0	29	0	0
T128	0	189	0	0
T129	0	214	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	10852	0	0
T2	4403	44	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	246	0	0
T27	0	14	0	0
T30	0	22	0	0
T59	0	189	0	0
T89	0	182	0	0
T123	0	23	0	0
T127	0	38	0	0
T128	0	178	0	0
T129	0	166	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	10800	0	0
T2	4403	31	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	222	0	0
T27	0	17	0	0
T30	0	42	0	0
T59	0	191	0	0
T89	0	130	0	0
T123	0	63	0	0
T127	0	36	0	0
T128	0	175	0	0
T129	0	187	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	10977	0	0
T2	4403	38	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	249	0	0
T27	0	11	0	0
T30	0	26	0	0
T59	0	171	0	0
T89	0	109	0	0
T123	0	55	0	0
T127	0	25	0	0
T128	0	177	0	0
T129	0	148	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	10958	0	0
T2	4403	55	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	215	0	0
T27	0	16	0	0
T30	0	20	0	0
T59	0	151	0	0
T89	0	145	0	0
T123	0	38	0	0
T127	0	28	0	0
T128	0	218	0	0
T129	0	166	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	11213	0	0
T2	4403	38	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	238	0	0
T27	0	11	0	0
T30	0	42	0	0
T59	0	174	0	0
T89	0	133	0	0
T123	0	54	0	0
T127	0	57	0	0
T128	0	178	0	0
T129	0	174	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	10910	0	0
T2	4403	26	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	249	0	0
T27	0	11	0	0
T30	0	34	0	0
T59	0	180	0	0
T89	0	181	0	0
T123	0	53	0	0
T127	0	23	0	0
T128	0	158	0	0
T129	0	151	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	10495	0	0
T2	4403	35	0	0
T3	2443	0	0	0
T4	4219	0	0	0
T5	8549	0	0	0
T6	80596	0	0	0
T7	25958	0	0	0
T8	53644	0	0	0
T9	53264	0	0	0
T10	2297	0	0	0
T11	18372	0	0	0
T23	0	244	0	0
T27	0	7	0	0
T30	0	26	0	0
T59	0	177	0	0
T89	0	153	0	0
T123	0	55	0	0
T127	0	35	0	0
T128	0	179	0	0
T129	0	159	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6326	0	0
T23	188519	180	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	8	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	31	0	0
T31	26169	0	0	0
T59	0	23	0	0
T89	0	86	0	0
T96	13518	0	0	0
T123	0	45	0	0
T124	0	30	0	0
T128	0	31	0	0
T129	0	29	0	0
T130	0	3	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6430	0	0
T23	188519	213	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	0	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	18	0	0
T31	26169	0	0	0
T59	0	33	0	0
T89	0	84	0	0
T96	13518	0	0	0
T101	0	205	0	0
T102	0	285	0	0
T123	0	33	0	0
T124	0	38	0	0
T128	0	33	0	0
T129	0	35	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6348	0	0
T23	188519	233	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	9	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	33	0	0
T31	26169	0	0	0
T59	0	20	0	0
T89	0	76	0	0
T96	13518	0	0	0
T123	0	58	0	0
T124	0	67	0	0
T128	0	40	0	0
T129	0	37	0	0
T130	0	9	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6489	0	0
T23	188519	200	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	5	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	42	0	0
T31	26169	0	0	0
T59	0	32	0	0
T89	0	59	0	0
T96	13518	0	0	0
T123	0	34	0	0
T124	0	65	0	0
T128	0	24	0	0
T129	0	31	0	0
T130	0	5	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6104	0	0
T23	188519	182	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	15	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	31	0	0
T31	26169	0	0	0
T59	0	28	0	0
T89	0	75	0	0
T96	13518	0	0	0
T123	0	56	0	0
T124	0	24	0	0
T128	0	32	0	0
T129	0	38	0	0
T130	0	1	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6241	0	0
T23	188519	160	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	10	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	40	0	0
T31	26169	0	0	0
T59	0	40	0	0
T89	0	82	0	0
T96	13518	0	0	0
T123	0	46	0	0
T124	0	42	0	0
T128	0	40	0	0
T129	0	37	0	0
T130	0	11	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6314	0	0
T23	188519	172	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	4	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	18	0	0
T31	26169	0	0	0
T59	0	36	0	0
T89	0	61	0	0
T96	13518	0	0	0
T123	0	57	0	0
T124	0	53	0	0
T128	0	23	0	0
T129	0	23	0	0
T130	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12476122	6217	0	0
T23	188519	209	0	0
T24	2458	0	0	0
T25	2107	0	0	0
T26	1324	0	0	0
T27	5764	1	0	0
T28	15661	0	0	0
T29	5469	0	0	0
T30	31048	35	0	0
T31	26169	0	0	0
T59	0	22	0	0
T89	0	57	0	0
T96	13518	0	0	0
T123	0	56	0	0
T124	0	44	0	0
T128	0	37	0	0
T129	0	21	0	0
T130	0	11	0	0