Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	574759	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

344034

1

T1

73

T2

59

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	489335	1			T1	99		T2	99		T3	9
values[0x0]	214924	1			T1	61		T2	54		T3	6
values[0x1]	214534	1			T1	52		T2	59		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	482282	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

436511

1

T1

90

T2

89

T3

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3364	1			T4	5		T5	180		T9	1
valid_sources[0x01]	3113	1			T4	5		T9	3		T21	11
valid_sources[0x02]	4771	1			T4	5		T21	10		T22	78
valid_sources[0x03]	3208	1			T4	3		T5	6		T6	4
valid_sources[0x04]	3206	1			T1	1		T4	1		T9	12
valid_sources[0x05]	3906	1			T1	2		T4	7		T11	2
valid_sources[0x06]	5420	1			T4	4		T21	6		T22	45
valid_sources[0x07]	2721	1			T1	2		T4	6		T6	1
valid_sources[0x08]	3487	1			T4	4		T11	4		T21	11
valid_sources[0x09]	3215	1			T4	2		T6	1		T11	2
valid_sources[0x0a]	3025	1			T4	1		T6	6		T9	2
valid_sources[0x0b]	3397	1			T1	3		T4	6		T9	1
valid_sources[0x0c]	3169	1			T4	5		T11	1		T21	18
valid_sources[0x0d]	2972	1			T1	1		T4	3		T11	1
valid_sources[0x0e]	3394	1			T1	1		T4	6		T6	6
valid_sources[0x0f]	2730	1			T1	1		T4	4		T6	5
valid_sources[0x10]	3333	1			T4	5		T6	5		T11	4
valid_sources[0x11]	2747	1			T1	1		T4	3		T11	6
valid_sources[0x12]	2906	1			T4	3		T5	3		T9	4
valid_sources[0x13]	3819	1			T4	7		T11	1		T21	10
valid_sources[0x14]	3578	1			T1	1		T4	3		T5	102
valid_sources[0x15]	3404	1			T1	1		T4	5		T5	5
valid_sources[0x16]	3509	1			T1	1		T4	9		T9	4
valid_sources[0x17]	5225	1			T4	5		T11	1		T21	8
valid_sources[0x18]	2954	1			T4	3		T6	12		T11	1
valid_sources[0x19]	4186	1			T1	1		T4	3		T11	2
valid_sources[0x1a]	3044	1			T1	1		T4	2		T5	1
valid_sources[0x1b]	3440	1			T1	1		T4	3		T21	6
valid_sources[0x1c]	3168	1			T1	2		T4	6		T6	1
valid_sources[0x1d]	2793	1			T4	2		T11	5		T21	14
valid_sources[0x1e]	3399	1			T4	5		T6	2		T11	3
valid_sources[0x1f]	3992	1			T1	3		T4	2		T11	2
valid_sources[0x20]	2903	1			T1	2		T4	5		T21	8
valid_sources[0x21]	4151	1			T4	5		T9	4		T21	17
valid_sources[0x22]	3217	1			T4	7		T6	6		T11	10
valid_sources[0x23]	3171	1			T1	1		T4	1		T21	11
valid_sources[0x24]	4574	1			T1	2		T4	2		T9	9
valid_sources[0x25]	3013	1			T4	6		T9	1		T21	12
valid_sources[0x26]	4822	1			T4	3		T9	1		T11	3
valid_sources[0x27]	4112	1			T4	3		T5	1		T9	9
valid_sources[0x28]	3095	1			T4	3		T21	7		T22	145
valid_sources[0x29]	3543	1			T4	9		T6	1		T11	1
valid_sources[0x2a]	3141	1			T4	3		T11	3		T21	14
valid_sources[0x2b]	3122	1			T4	2		T21	12		T22	77
valid_sources[0x2c]	5546	1			T4	3		T21	14		T22	32
valid_sources[0x2d]	3164	1			T4	3		T11	4		T21	10
valid_sources[0x2e]	3623	1			T1	1		T4	2		T21	13
valid_sources[0x2f]	3093	1			T4	3		T6	6		T11	3
valid_sources[0x30]	5903	1			T1	7		T4	9		T6	5
valid_sources[0x31]	3131	1			T4	1		T11	1		T21	7
valid_sources[0x32]	3596	1			T1	3		T4	7		T9	3
valid_sources[0x33]	3527	1			T1	2		T2	212		T4	1
valid_sources[0x34]	2918	1			T4	1		T11	1		T21	14
valid_sources[0x35]	3378	1			T1	1		T4	4		T11	5
valid_sources[0x36]	3560	1			T4	1		T5	3		T9	3
valid_sources[0x37]	3140	1			T1	1		T4	2		T11	4
valid_sources[0x38]	3092	1			T4	6		T9	1		T21	9
valid_sources[0x39]	3573	1			T4	4		T9	6		T11	2
valid_sources[0x3a]	2698	1			T4	6		T9	6		T21	12
valid_sources[0x3b]	3314	1			T1	3		T4	4		T6	4
valid_sources[0x3c]	3414	1			T4	5		T11	3		T21	14
valid_sources[0x3d]	3985	1			T4	4		T21	7		T22	106
valid_sources[0x3e]	3743	1			T1	2		T4	11		T5	3
valid_sources[0x3f]	3255	1			T4	5		T9	5		T11	2
valid_sources[0x40]	3169	1			T1	4		T4	7		T6	1
valid_sources[0x41]	3175	1			T4	4		T21	19		T22	82
valid_sources[0x42]	3748	1			T4	1		T11	2		T21	11
valid_sources[0x43]	3242	1			T1	2		T4	6		T8	1
valid_sources[0x44]	4421	1			T4	1		T5	101		T9	4
valid_sources[0x45]	2928	1			T4	3		T21	16		T22	59
valid_sources[0x46]	3162	1			T4	8		T9	4		T21	9
valid_sources[0x47]	4476	1			T4	5		T5	1		T6	2
valid_sources[0x48]	3293	1			T4	2		T9	1		T21	13
valid_sources[0x49]	3086	1			T1	4		T4	4		T21	13
valid_sources[0x4a]	4336	1			T4	5		T11	2		T21	11
valid_sources[0x4b]	4041	1			T1	3		T4	3		T9	2
valid_sources[0x4c]	4224	1			T1	7		T4	9		T9	9
valid_sources[0x4d]	2824	1			T4	4		T9	4		T11	1
valid_sources[0x4e]	4534	1			T4	6		T5	104		T9	2
valid_sources[0x4f]	3278	1			T4	3		T6	5		T9	1
valid_sources[0x50]	3208	1			T1	1		T4	7		T11	2
valid_sources[0x51]	3673	1			T1	8		T4	3		T9	3
valid_sources[0x52]	7557	1			T4	3		T21	12		T22	89
valid_sources[0x53]	3445	1			T4	5		T6	3		T9	10
valid_sources[0x54]	2971	1			T1	2		T4	2		T9	3
valid_sources[0x55]	2874	1			T4	3		T6	4		T11	2
valid_sources[0x56]	3309	1			T4	4		T11	2		T21	14
valid_sources[0x57]	2844	1			T4	4		T5	9		T21	8
valid_sources[0x58]	3548	1			T4	2		T9	8		T11	1
valid_sources[0x59]	2829	1			T4	2		T9	2		T11	1
valid_sources[0x5a]	7184	1			T1	5		T4	3		T5	2
valid_sources[0x5b]	3166	1			T4	6		T6	8		T11	3
valid_sources[0x5c]	2832	1			T4	4		T6	5		T21	8
valid_sources[0x5d]	2924	1			T4	4		T9	3		T21	10
valid_sources[0x5e]	3396	1			T4	5		T9	4		T21	9
valid_sources[0x5f]	3254	1			T4	8		T9	2		T11	1
valid_sources[0x60]	3445	1			T4	13		T6	1		T11	2
valid_sources[0x61]	2856	1			T1	5		T4	2		T9	6
valid_sources[0x62]	3327	1			T1	1		T3	21		T5	9
valid_sources[0x63]	6575	1			T4	4		T5	318		T11	3
valid_sources[0x64]	3286	1			T1	2		T4	5		T9	1
valid_sources[0x65]	3059	1			T4	1		T11	1		T21	15
valid_sources[0x66]	3023	1			T1	2		T4	2		T6	2
valid_sources[0x67]	2968	1			T1	1		T4	2		T6	2
valid_sources[0x68]	6582	1			T4	6		T5	108		T6	4
valid_sources[0x69]	6191	1			T4	6		T9	1		T11	3
valid_sources[0x6a]	3699	1			T1	1		T4	3		T6	1
valid_sources[0x6b]	4101	1			T4	4		T11	1		T21	15
valid_sources[0x6c]	2923	1			T4	7		T9	1		T21	9
valid_sources[0x6d]	3511	1			T4	1		T6	3		T9	3
valid_sources[0x6e]	3106	1			T4	7		T11	2		T21	9
valid_sources[0x6f]	4081	1			T4	4		T9	13		T11	3
valid_sources[0x70]	3730	1			T4	5		T11	4		T21	13
valid_sources[0x71]	3098	1			T1	7		T4	8		T21	13
valid_sources[0x72]	3208	1			T1	2		T4	3		T11	2
valid_sources[0x73]	3014	1			T1	2		T4	3		T9	2
valid_sources[0x74]	3360	1			T1	2		T4	5		T9	2
valid_sources[0x75]	6341	1			T4	7		T11	3		T21	11
valid_sources[0x76]	4270	1			T4	3		T11	2		T21	11
valid_sources[0x77]	3561	1			T1	5		T4	6		T6	1
valid_sources[0x78]	2711	1			T1	1		T4	7		T11	1
valid_sources[0x79]	2903	1			T1	4		T4	6		T21	8
valid_sources[0x7a]	6474	1			T1	5		T4	1		T6	4
valid_sources[0x7b]	6382	1			T4	1		T9	2		T21	18
valid_sources[0x7c]	2967	1			T1	1		T4	4		T9	2
valid_sources[0x7d]	3198	1			T4	5		T6	1		T9	3
valid_sources[0x7e]	3409	1			T4	3		T9	1		T21	14
valid_sources[0x7f]	3772	1			T1	1		T4	4		T21	10
valid_sources[0x80]	3670	1			T4	1		T6	2		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

229844

1

T1

48

T2

35

T3

3

values[0x0]

all_enables

biggest_size

74660

1

T1

15

T2

19

T3

1

values[0x1]

all_enables

biggest_size

39530

1

T1

10

T2

5

T4

46