Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T5,T6
1	0	Covered	T5,T11,T21

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	49818040	7948	0	0
CascadeEffAonToRstPorAboveRise_A	49818040	7948	0	0
CascadeEffAonToRstPorIoAboveFall_A	47823502	7948	0	0
CascadeEffAonToRstPorIoAboveRise_A	47823502	7948	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	23912966	7948	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	23912966	7948	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	11955875	7948	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	11955875	7948	0	0
CascadeEffAonToRstPorUcbAboveFall_A	23912598	7948	0	0
CascadeEffAonToRstPorUcbAboveRise_A	23912598	7948	0	0
CascadeLcToLcAboveFall_A	49818040	20161	0	0
CascadeLcToLcAboveRise_A	49818040	20161	0	0
CascadeLcToLcAonAboveFall_A	1509097	20161	0	0
CascadeLcToLcAonAboveRise_A	1509097	20161	0	0
CascadeLcToLcShadowedAboveFall_A	49818040	20161	0	0
CascadeLcToLcShadowedAboveRise_A	49818040	20161	0	0
CascadePorToAonAboveFall_A	1509097	6391	0	0
CascadeSysToSysAboveFall_A	49818040	20161	0	0
CascadeSysToSysAboveRise_A	49818040	20161	0	0
ScanRstToAonRise_A	1509097	185	0	0
StablePorToAonRise_A	1509097	7948	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10609099	20161	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10609099	20161	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10609099	20161	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10609099	20161	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	11955875	20161	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	11955875	20161	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10609099	20161	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10609099	20161	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10609099	20161	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10609099	20161	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	7948	0	0
T1	10820	2	0	0
T2	17831	2	0	0
T3	6577	1	0	0
T4	15697	1	0	0
T5	152495	17	0	0
T6	10659	2	0	0
T7	188459	27	0	0
T8	20317	2	0	0
T9	19942	2	0	0
T10	12919	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	7948	0	0
T1	10820	2	0	0
T2	17831	2	0	0
T3	6577	1	0	0
T4	15697	1	0	0
T5	152495	17	0	0
T6	10659	2	0	0
T7	188459	27	0	0
T8	20317	2	0	0
T9	19942	2	0	0
T10	12919	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47823502	7948	0	0
T1	10387	2	0	0
T2	17114	2	0	0
T3	6313	1	0	0
T4	15068	1	0	0
T5	146382	17	0	0
T6	10227	2	0	0
T7	180878	27	0	0
T8	19503	2	0	0
T9	19144	2	0	0
T10	12402	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47823502	7948	0	0
T1	10387	2	0	0
T2	17114	2	0	0
T3	6313	1	0	0
T4	15068	1	0	0
T5	146382	17	0	0
T6	10227	2	0	0
T7	180878	27	0	0
T8	19503	2	0	0
T9	19144	2	0	0
T10	12402	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912966	7948	0	0
T1	5193	2	0	0
T2	8557	2	0	0
T3	3156	1	0	0
T4	7534	1	0	0
T5	73195	17	0	0
T6	5115	2	0	0
T7	90446	27	0	0
T8	9752	2	0	0
T9	9571	2	0	0
T10	6200	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912966	7948	0	0
T1	5193	2	0	0
T2	8557	2	0	0
T3	3156	1	0	0
T4	7534	1	0	0
T5	73195	17	0	0
T6	5115	2	0	0
T7	90446	27	0	0
T8	9752	2	0	0
T9	9571	2	0	0
T10	6200	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	7948	0	0
T1	2594	2	0	0
T2	4278	2	0	0
T3	1578	1	0	0
T4	3766	1	0	0
T5	36594	17	0	0
T6	2555	2	0	0
T7	45226	27	0	0
T8	4876	2	0	0
T9	4785	2	0	0
T10	3100	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	7948	0	0
T1	2594	2	0	0
T2	4278	2	0	0
T3	1578	1	0	0
T4	3766	1	0	0
T5	36594	17	0	0
T6	2555	2	0	0
T7	45226	27	0	0
T8	4876	2	0	0
T9	4785	2	0	0
T10	3100	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912598	7948	0	0
T1	5192	2	0	0
T2	8559	2	0	0
T3	3156	1	0	0
T4	7534	1	0	0
T5	73192	17	0	0
T6	5112	2	0	0
T7	90468	27	0	0
T8	9752	2	0	0
T9	9572	2	0	0
T10	6200	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912598	7948	0	0
T1	5192	2	0	0
T2	8559	2	0	0
T3	3156	1	0	0
T4	7534	1	0	0
T5	73192	17	0	0
T6	5112	2	0	0
T7	90468	27	0	0
T8	9752	2	0	0
T9	9572	2	0	0
T10	6200	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	20161	0	0
T1	10820	6	0	0
T2	17831	6	0	0
T3	6577	2	0	0
T4	15697	1	0	0
T5	152495	45	0	0
T6	10659	6	0	0
T7	188459	102	0	0
T8	20317	2	0	0
T9	19942	6	0	0
T10	12919	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	20161	0	0
T1	10820	6	0	0
T2	17831	6	0	0
T3	6577	2	0	0
T4	15697	1	0	0
T5	152495	45	0	0
T6	10659	6	0	0
T7	188459	102	0	0
T8	20317	2	0	0
T9	19942	6	0	0
T10	12919	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	20161	0	0
T1	322	6	0	0
T2	534	6	0	0
T3	195	2	0	0
T4	469	1	0	0
T5	4634	45	0	0
T6	319	6	0	0
T7	5668	102	0	0
T8	607	2	0	0
T9	597	6	0	0
T10	385	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	20161	0	0
T1	322	6	0	0
T2	534	6	0	0
T3	195	2	0	0
T4	469	1	0	0
T5	4634	45	0	0
T6	319	6	0	0
T7	5668	102	0	0
T8	607	2	0	0
T9	597	6	0	0
T10	385	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	20161	0	0
T1	10820	6	0	0
T2	17831	6	0	0
T3	6577	2	0	0
T4	15697	1	0	0
T5	152495	45	0	0
T6	10659	6	0	0
T7	188459	102	0	0
T8	20317	2	0	0
T9	19942	6	0	0
T10	12919	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	20161	0	0
T1	10820	6	0	0
T2	17831	6	0	0
T3	6577	2	0	0
T4	15697	1	0	0
T5	152495	45	0	0
T6	10659	6	0	0
T7	188459	102	0	0
T8	20317	2	0	0
T9	19942	6	0	0
T10	12919	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	6391	0	0
T1	322	1	0	0
T2	534	1	0	0
T3	195	1	0	0
T4	469	1	0	0
T5	4634	7	0	0
T6	319	1	0	0
T7	5668	27	0	0
T8	607	18	0	0
T9	597	1	0	0
T10	385	7	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	20161	0	0
T1	10820	6	0	0
T2	17831	6	0	0
T3	6577	2	0	0
T4	15697	1	0	0
T5	152495	45	0	0
T6	10659	6	0	0
T7	188459	102	0	0
T8	20317	2	0	0
T9	19942	6	0	0
T10	12919	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49818040	20161	0	0
T1	10820	6	0	0
T2	17831	6	0	0
T3	6577	2	0	0
T4	15697	1	0	0
T5	152495	45	0	0
T6	10659	6	0	0
T7	188459	102	0	0
T8	20317	2	0	0
T9	19942	6	0	0
T10	12919	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	185	0	0
T6	319	1	0	0
T7	5668	0	0	0
T8	607	0	0	0
T9	597	1	0	0
T10	385	0	0	0
T11	778	0	0	0
T20	226	0	0	0
T21	2854	0	0	0
T22	19930	3	0	0
T23	197	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T80	0	2	0	0
T85	0	7	0	0
T93	0	1	0	0
T94	0	3	0	0
T129	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	7948	0	0
T1	322	2	0	0
T2	534	2	0	0
T3	195	1	0	0
T4	469	1	0	0
T5	4634	17	0	0
T6	319	2	0	0
T7	5668	27	0	0
T8	607	2	0	0
T9	597	2	0	0
T10	385	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	20161	0	0
T1	2594	6	0	0
T2	4278	6	0	0
T3	1578	2	0	0
T4	3766	1	0	0
T5	36594	45	0	0
T6	2555	6	0	0
T7	45226	102	0	0
T8	4876	2	0	0
T9	4785	6	0	0
T10	3100	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	20161	0	0
T1	2594	6	0	0
T2	4278	6	0	0
T3	1578	2	0	0
T4	3766	1	0	0
T5	36594	45	0	0
T6	2555	6	0	0
T7	45226	102	0	0
T8	4876	2	0	0
T9	4785	6	0	0
T10	3100	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10609099	20161	0	0
T1	2451	6	0	0
T2	4034	6	0	0
T3	1409	2	0	0
T4	3700	1	0	0
T5	32801	45	0	0
T6	2270	6	0	0
T7	41911	102	0	0
T8	4761	2	0	0
T9	4687	6	0	0
T10	3009	2	0	0