Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T20,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T22,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T22
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T22,T24
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T22
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	11955875	13069	0	0
gen_assertions[0].RstEnOn_A	11955875	1010	0	0
gen_assertions[0].RstNOff_A	11955875	13069	0	0
gen_assertions[0].RstNOn_A	11955875	1010	0	0
gen_assertions[1].RstEnOff_A	47823502	11895	0	0
gen_assertions[1].RstEnOn_A	47823502	978	0	0
gen_assertions[1].RstNOff_A	47823502	11895	0	0
gen_assertions[1].RstNOn_A	47823502	978	0	0
gen_assertions[2].RstEnOff_A	23912966	11962	0	0
gen_assertions[2].RstEnOn_A	23912966	1002	0	0
gen_assertions[2].RstNOff_A	23912966	11962	0	0
gen_assertions[2].RstNOn_A	23912966	1002	0	0
gen_assertions[3].RstEnOff_A	23912598	12002	0	0
gen_assertions[3].RstEnOn_A	23912598	1017	0	0
gen_assertions[3].RstNOff_A	23912598	12002	0	0
gen_assertions[3].RstNOn_A	23912598	1017	0	0
gen_assertions[4].RstEnOff_A	1509097	19848	0	0
gen_assertions[4].RstEnOn_A	1509097	1048	0	0
gen_assertions[4].RstNOff_A	1509097	19848	0	0
gen_assertions[4].RstNOn_A	1509097	1048	0	0
gen_assertions[5].RstEnOff_A	11955875	13319	0	0
gen_assertions[5].RstEnOn_A	11955875	1152	0	0
gen_assertions[5].RstNOff_A	11955875	13319	0	0
gen_assertions[5].RstNOn_A	11955875	1152	0	0
gen_assertions[6].RstEnOff_A	11955875	13349	0	0
gen_assertions[6].RstEnOn_A	11955875	1170	0	0
gen_assertions[6].RstNOff_A	11955875	13349	0	0
gen_assertions[6].RstNOn_A	11955875	1170	0	0
gen_assertions[7].RstEnOff_A	11955875	13397	0	0
gen_assertions[7].RstEnOn_A	11955875	1225	0	0
gen_assertions[7].RstNOff_A	11955875	13397	0	0
gen_assertions[7].RstNOn_A	11955875	1225	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13069	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	6	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1010	0	0
T4	3766	6	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	0	0	0
T20	1818	3	0	0
T21	22530	0	0	0
T22	0	31	0	0
T24	0	1	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T77	0	4	0	0
T78	0	7	0	0
T79	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13069	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	6	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1010	0	0
T4	3766	6	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	0	0	0
T20	1818	3	0	0
T21	22530	0	0	0
T22	0	31	0	0
T24	0	1	0	0
T38	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T77	0	4	0	0
T78	0	7	0	0
T79	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47823502	11895	0	0
T1	10387	4	0	0
T2	17114	4	0	0
T3	6313	1	0	0
T4	15068	9	0	0
T5	146382	25	0	0
T6	10227	4	0	0
T7	180878	65	0	0
T8	19503	0	0	0
T9	19144	5	0	0
T10	12402	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47823502	978	0	0
T4	15068	9	0	0
T5	146382	0	0	0
T6	10227	0	0	0
T7	180878	0	0	0
T8	19503	0	0	0
T9	19144	1	0	0
T10	12402	0	0	0
T11	24964	0	0	0
T20	7278	0	0	0
T21	90102	0	0	0
T22	0	26	0	0
T24	0	2	0	0
T39	0	3	0	0
T77	0	4	0	0
T78	0	6	0	0
T80	0	15	0	0
T81	0	2	0	0
T82	0	6	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47823502	11895	0	0
T1	10387	4	0	0
T2	17114	4	0	0
T3	6313	1	0	0
T4	15068	9	0	0
T5	146382	25	0	0
T6	10227	4	0	0
T7	180878	65	0	0
T8	19503	0	0	0
T9	19144	5	0	0
T10	12402	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47823502	978	0	0
T4	15068	9	0	0
T5	146382	0	0	0
T6	10227	0	0	0
T7	180878	0	0	0
T8	19503	0	0	0
T9	19144	1	0	0
T10	12402	0	0	0
T11	24964	0	0	0
T20	7278	0	0	0
T21	90102	0	0	0
T22	0	26	0	0
T24	0	2	0	0
T39	0	3	0	0
T77	0	4	0	0
T78	0	6	0	0
T80	0	15	0	0
T81	0	2	0	0
T82	0	6	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912966	11962	0	0
T1	5193	4	0	0
T2	8557	4	0	0
T3	3156	1	0	0
T4	7534	9	0	0
T5	73195	25	0	0
T6	5115	4	0	0
T7	90446	65	0	0
T8	9752	0	0	0
T9	9571	4	0	0
T10	6200	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912966	1002	0	0
T4	7534	9	0	0
T5	73195	0	0	0
T6	5115	0	0	0
T7	90446	0	0	0
T8	9752	0	0	0
T9	9571	0	0	0
T10	6200	0	0	0
T11	12482	0	0	0
T20	3638	0	0	0
T21	45065	0	0	0
T22	0	30	0	0
T24	0	2	0	0
T38	0	1	0	0
T39	0	5	0	0
T77	0	6	0	0
T78	0	2	0	0
T80	0	16	0	0
T81	0	3	0	0
T83	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912966	11962	0	0
T1	5193	4	0	0
T2	8557	4	0	0
T3	3156	1	0	0
T4	7534	9	0	0
T5	73195	25	0	0
T6	5115	4	0	0
T7	90446	65	0	0
T8	9752	0	0	0
T9	9571	4	0	0
T10	6200	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912966	1002	0	0
T4	7534	9	0	0
T5	73195	0	0	0
T6	5115	0	0	0
T7	90446	0	0	0
T8	9752	0	0	0
T9	9571	0	0	0
T10	6200	0	0	0
T11	12482	0	0	0
T20	3638	0	0	0
T21	45065	0	0	0
T22	0	30	0	0
T24	0	2	0	0
T38	0	1	0	0
T39	0	5	0	0
T77	0	6	0	0
T78	0	2	0	0
T80	0	16	0	0
T81	0	3	0	0
T83	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912598	12002	0	0
T1	5192	4	0	0
T2	8559	4	0	0
T3	3156	1	0	0
T4	7534	12	0	0
T5	73192	25	0	0
T6	5112	4	0	0
T7	90468	65	0	0
T8	9752	0	0	0
T9	9572	5	0	0
T10	6200	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912598	1017	0	0
T4	7534	12	0	0
T5	73192	0	0	0
T6	5112	0	0	0
T7	90468	0	0	0
T8	9752	0	0	0
T9	9572	1	0	0
T10	6200	0	0	0
T11	12483	0	0	0
T20	3638	0	0	0
T21	45057	0	0	0
T22	0	30	0	0
T24	0	3	0	0
T38	0	1	0	0
T39	0	6	0	0
T41	0	1	0	0
T77	0	6	0	0
T79	0	1	0	0
T80	0	19	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912598	12002	0	0
T1	5192	4	0	0
T2	8559	4	0	0
T3	3156	1	0	0
T4	7534	12	0	0
T5	73192	25	0	0
T6	5112	4	0	0
T7	90468	65	0	0
T8	9752	0	0	0
T9	9572	5	0	0
T10	6200	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	23912598	1017	0	0
T4	7534	12	0	0
T5	73192	0	0	0
T6	5112	0	0	0
T7	90468	0	0	0
T8	9752	0	0	0
T9	9572	1	0	0
T10	6200	0	0	0
T11	12483	0	0	0
T20	3638	0	0	0
T21	45057	0	0	0
T22	0	30	0	0
T24	0	3	0	0
T38	0	1	0	0
T39	0	6	0	0
T41	0	1	0	0
T77	0	6	0	0
T79	0	1	0	0
T80	0	19	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	19848	0	0
T1	322	5	0	0
T2	534	6	0	0
T3	195	2	0	0
T4	469	12	0	0
T5	4634	43	0	0
T6	319	5	0	0
T7	5668	92	0	0
T8	607	2	0	0
T9	597	7	0	0
T10	385	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	1048	0	0
T4	469	11	0	0
T5	4634	0	0	0
T6	319	0	0	0
T7	5668	0	0	0
T8	607	0	0	0
T9	597	1	0	0
T10	385	0	0	0
T11	778	0	0	0
T20	226	0	0	0
T21	2854	0	0	0
T22	0	20	0	0
T24	0	5	0	0
T39	0	6	0	0
T41	0	1	0	0
T77	0	7	0	0
T80	0	11	0	0
T81	0	5	0	0
T82	0	10	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	19848	0	0
T1	322	5	0	0
T2	534	6	0	0
T3	195	2	0	0
T4	469	12	0	0
T5	4634	43	0	0
T6	319	5	0	0
T7	5668	92	0	0
T8	607	2	0	0
T9	597	7	0	0
T10	385	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1509097	1048	0	0
T4	469	11	0	0
T5	4634	0	0	0
T6	319	0	0	0
T7	5668	0	0	0
T8	607	0	0	0
T9	597	1	0	0
T10	385	0	0	0
T11	778	0	0	0
T20	226	0	0	0
T21	2854	0	0	0
T22	0	20	0	0
T24	0	5	0	0
T39	0	6	0	0
T41	0	1	0	0
T77	0	7	0	0
T80	0	11	0	0
T81	0	5	0	0
T82	0	10	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13319	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	12	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	5	0	0
T20	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1152	0	0
T4	3766	12	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	1	0	0
T20	1818	0	0	0
T21	22530	0	0	0
T22	0	30	0	0
T24	0	5	0	0
T38	0	1	0	0
T39	0	9	0	0
T77	0	9	0	0
T80	0	13	0	0
T81	0	6	0	0
T82	0	13	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13319	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	12	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	5	0	0
T20	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1152	0	0
T4	3766	12	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	1	0	0
T20	1818	0	0	0
T21	22530	0	0	0
T22	0	30	0	0
T24	0	5	0	0
T38	0	1	0	0
T39	0	9	0	0
T77	0	9	0	0
T80	0	13	0	0
T81	0	6	0	0
T82	0	13	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13349	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	12	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1170	0	0
T4	3766	12	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	0	0	0
T20	1818	0	0	0
T21	22530	0	0	0
T22	0	24	0	0
T24	0	7	0	0
T39	0	9	0	0
T77	0	10	0	0
T80	0	16	0	0
T81	0	6	0	0
T82	0	14	0	0
T84	0	8	0	0
T85	0	24	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13349	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	12	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	4	0	0
T20	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1170	0	0
T4	3766	12	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	0	0	0
T20	1818	0	0	0
T21	22530	0	0	0
T22	0	24	0	0
T24	0	7	0	0
T39	0	9	0	0
T77	0	10	0	0
T80	0	16	0	0
T81	0	6	0	0
T82	0	14	0	0
T84	0	8	0	0
T85	0	24	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13397	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	16	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	5	0	0
T20	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1225	0	0
T4	3766	16	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	1	0	0
T20	1818	0	0	0
T21	22530	0	0	0
T22	0	27	0	0
T24	0	8	0	0
T39	0	10	0	0
T77	0	13	0	0
T79	0	1	0	0
T80	0	15	0	0
T81	0	8	0	0
T82	0	15	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	13397	0	0
T1	2594	4	0	0
T2	4278	4	0	0
T3	1578	1	0	0
T4	3766	16	0	0
T5	36594	28	0	0
T6	2555	4	0	0
T7	45226	75	0	0
T8	4876	0	0	0
T9	4785	4	0	0
T10	3100	0	0	0
T11	0	5	0	0
T20	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11955875	1225	0	0
T4	3766	16	0	0
T5	36594	0	0	0
T6	2555	0	0	0
T7	45226	0	0	0
T8	4876	0	0	0
T9	4785	0	0	0
T10	3100	0	0	0
T11	6242	1	0	0
T20	1818	0	0	0
T21	22530	0	0	0
T22	0	27	0	0
T24	0	8	0	0
T39	0	10	0	0
T77	0	13	0	0
T79	0	1	0	0
T80	0	15	0	0
T81	0	8	0	0
T82	0	15	0	0