Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11317779	8102	0	0
alert_regwen_rd_A	11317779	4706	0	0
cpu_regwen_rd_A	11317779	4576	0	0
sw_rst_ctrl_n_0_rd_A	11317779	11018	0	0
sw_rst_ctrl_n_1_rd_A	11317779	11275	0	0
sw_rst_ctrl_n_2_rd_A	11317779	10827	0	0
sw_rst_ctrl_n_3_rd_A	11317779	10873	0	0
sw_rst_ctrl_n_4_rd_A	11317779	11119	0	0
sw_rst_ctrl_n_5_rd_A	11317779	11079	0	0
sw_rst_ctrl_n_6_rd_A	11317779	11220	0	0
sw_rst_ctrl_n_7_rd_A	11317779	11158	0	0
sw_rst_regwen_0_rd_A	11317779	5394	0	0
sw_rst_regwen_1_rd_A	11317779	5515	0	0
sw_rst_regwen_2_rd_A	11317779	5555	0	0
sw_rst_regwen_3_rd_A	11317779	5344	0	0
sw_rst_regwen_4_rd_A	11317779	5434	0	0
sw_rst_regwen_5_rd_A	11317779	5662	0	0
sw_rst_regwen_6_rd_A	11317779	5454	0	0
sw_rst_regwen_7_rd_A	11317779	5484	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	8102	0	0
T54	10851	1	0	0
T56	11628	2	0	0
T57	6976	190	0	0
T58	3154	14	0	0
T59	2666	6	0	0
T60	11548	2	0	0
T61	11756	1	0	0
T86	10625	399	0	0
T87	2349	202	0	0
T88	3868	112	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	4706	0	0
T5	32801	39	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	0	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T93	0	49	0	0
T96	0	171	0	0
T120	0	27	0	0
T121	0	219	0	0
T122	0	243	0	0
T123	0	32	0	0
T124	0	44	0	0
T125	0	43	0	0
T126	0	262	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	4576	0	0
T5	32801	43	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	0	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T93	0	48	0	0
T96	0	167	0	0
T120	0	57	0	0
T121	0	161	0	0
T122	0	235	0	0
T123	0	45	0	0
T124	0	32	0	0
T125	0	33	0	0
T126	0	243	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	11018	0	0
T5	32801	50	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	21	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	120	0	0
T38	0	16	0	0
T77	0	166	0	0
T82	0	205	0	0
T84	0	159	0	0
T93	0	57	0	0
T127	0	194	0	0
T128	0	193	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	11275	0	0
T5	32801	78	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	16	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	121	0	0
T38	0	6	0	0
T77	0	164	0	0
T82	0	233	0	0
T84	0	195	0	0
T93	0	56	0	0
T127	0	168	0	0
T128	0	218	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	10827	0	0
T5	32801	29	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	15	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	106	0	0
T38	0	11	0	0
T77	0	188	0	0
T82	0	207	0	0
T84	0	151	0	0
T93	0	76	0	0
T127	0	196	0	0
T128	0	244	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	10873	0	0
T5	32801	49	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	5	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	107	0	0
T38	0	3	0	0
T77	0	169	0	0
T82	0	210	0	0
T84	0	177	0	0
T93	0	69	0	0
T127	0	232	0	0
T128	0	219	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	11119	0	0
T5	32801	57	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	10	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	111	0	0
T38	0	28	0	0
T77	0	163	0	0
T82	0	227	0	0
T84	0	148	0	0
T93	0	77	0	0
T127	0	218	0	0
T128	0	191	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	11079	0	0
T5	32801	41	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	15	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	146	0	0
T38	0	10	0	0
T77	0	153	0	0
T82	0	215	0	0
T84	0	169	0	0
T93	0	67	0	0
T127	0	191	0	0
T128	0	206	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	11220	0	0
T5	32801	67	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	14	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	112	0	0
T38	0	15	0	0
T77	0	161	0	0
T82	0	216	0	0
T84	0	162	0	0
T93	0	69	0	0
T127	0	159	0	0
T128	0	195	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	11158	0	0
T5	32801	69	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	9	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	130	0	0
T38	0	4	0	0
T77	0	174	0	0
T82	0	213	0	0
T84	0	190	0	0
T93	0	72	0	0
T127	0	174	0	0
T128	0	235	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5394	0	0
T5	32801	40	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	9	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	36	0	0
T38	0	1	0	0
T77	0	39	0	0
T82	0	31	0	0
T84	0	32	0	0
T93	0	66	0	0
T127	0	44	0	0
T128	0	26	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5515	0	0
T5	32801	60	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	4	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	42	0	0
T38	0	2	0	0
T77	0	56	0	0
T82	0	37	0	0
T84	0	24	0	0
T93	0	68	0	0
T127	0	33	0	0
T128	0	35	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5555	0	0
T5	32801	39	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	7	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	43	0	0
T38	0	13	0	0
T77	0	33	0	0
T82	0	30	0	0
T84	0	49	0	0
T93	0	75	0	0
T127	0	12	0	0
T128	0	25	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5344	0	0
T5	32801	51	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	6	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	22	0	0
T38	0	4	0	0
T77	0	31	0	0
T82	0	31	0	0
T84	0	24	0	0
T93	0	55	0	0
T127	0	37	0	0
T128	0	35	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5434	0	0
T5	32801	67	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	10	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	17	0	0
T38	0	9	0	0
T77	0	23	0	0
T82	0	38	0	0
T84	0	34	0	0
T93	0	76	0	0
T127	0	32	0	0
T128	0	50	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5662	0	0
T5	32801	50	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	3	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	35	0	0
T77	0	45	0	0
T82	0	26	0	0
T84	0	31	0	0
T93	0	65	0	0
T96	0	166	0	0
T127	0	41	0	0
T128	0	39	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5454	0	0
T5	32801	47	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	5	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	17	0	0
T38	0	3	0	0
T77	0	42	0	0
T82	0	52	0	0
T84	0	36	0	0
T93	0	36	0	0
T127	0	30	0	0
T128	0	28	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11317779	5484	0	0
T5	32801	40	0	0
T6	2270	0	0	0
T7	41911	0	0	0
T8	4761	0	0	0
T9	4687	0	0	0
T10	3009	0	0	0
T11	5854	8	0	0
T20	1468	0	0	0
T21	17264	0	0	0
T22	126500	0	0	0
T24	0	47	0	0
T77	0	54	0	0
T82	0	21	0	0
T84	0	29	0	0
T93	0	56	0	0
T96	0	145	0	0
T127	0	36	0	0
T128	0	31	0	0