Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	659312	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

394159

1

T1

1084

T3

3724

T4

135

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	562436	1			T1	1500		T2	1		T3	5676
values[0x0]	245115	1			T1	835		T3	2366		T4	91
values[0x1]	245920	1			T1	865		T3	2306		T4	102

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	553157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

500314

1

T1

1426

T3

4828

T4

166

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3722	1			T3	53		T6	32		T7	10
valid_sources[0x01]	3670	1			T3	38		T6	32		T7	18
valid_sources[0x02]	4900	1			T3	35		T6	30		T7	13
valid_sources[0x03]	4020	1			T3	52		T6	32		T7	8
valid_sources[0x04]	3668	1			T3	44		T6	36		T7	7
valid_sources[0x05]	3552	1			T3	35		T6	23		T7	17
valid_sources[0x06]	3465	1			T3	41		T6	27		T7	9
valid_sources[0x07]	3462	1			T3	40		T6	31		T7	16
valid_sources[0x08]	3807	1			T3	40		T6	39		T7	13
valid_sources[0x09]	3558	1			T3	45		T6	33		T7	8
valid_sources[0x0a]	3576	1			T3	30		T6	26		T7	17
valid_sources[0x0b]	4738	1			T3	47		T6	35		T7	11
valid_sources[0x0c]	3971	1			T3	33		T6	46		T7	9
valid_sources[0x0d]	3378	1			T3	38		T6	14		T7	17
valid_sources[0x0e]	3861	1			T3	43		T6	39		T7	9
valid_sources[0x0f]	4349	1			T3	30		T6	22		T7	12
valid_sources[0x10]	3682	1			T3	30		T6	27		T7	10
valid_sources[0x11]	3699	1			T3	41		T6	43		T7	18
valid_sources[0x12]	6144	1			T3	43		T6	29		T7	15
valid_sources[0x13]	3629	1			T3	38		T6	35		T7	12
valid_sources[0x14]	6827	1			T3	27		T6	30		T7	14
valid_sources[0x15]	7982	1			T3	54		T6	34		T7	14
valid_sources[0x16]	3681	1			T3	45		T6	25		T7	11
valid_sources[0x17]	3953	1			T3	47		T6	26		T7	14
valid_sources[0x18]	4911	1			T3	44		T6	33		T7	14
valid_sources[0x19]	3174	1			T3	27		T6	32		T7	14
valid_sources[0x1a]	3306	1			T3	44		T6	33		T7	7
valid_sources[0x1b]	3760	1			T3	35		T6	39		T7	12
valid_sources[0x1c]	3169	1			T3	53		T6	40		T7	9
valid_sources[0x1d]	6799	1			T3	42		T6	42		T7	17
valid_sources[0x1e]	4040	1			T3	31		T6	30		T7	10
valid_sources[0x1f]	4811	1			T3	54		T6	37		T7	12
valid_sources[0x20]	4603	1			T3	48		T6	31		T7	12
valid_sources[0x21]	3244	1			T3	41		T6	41		T7	8
valid_sources[0x22]	4047	1			T3	44		T6	28		T7	14
valid_sources[0x23]	4125	1			T3	47		T6	41		T7	11
valid_sources[0x24]	4039	1			T3	61		T6	25		T7	12
valid_sources[0x25]	4090	1			T3	49		T6	20		T7	15
valid_sources[0x26]	3646	1			T3	38		T6	27		T7	12
valid_sources[0x27]	5022	1			T3	42		T6	26		T7	7
valid_sources[0x28]	4948	1			T3	53		T6	33		T7	10
valid_sources[0x29]	5096	1			T3	50		T6	26		T7	7
valid_sources[0x2a]	4201	1			T3	43		T6	32		T7	10
valid_sources[0x2b]	4626	1			T3	38		T6	35		T7	13
valid_sources[0x2c]	3194	1			T3	49		T6	34		T7	10
valid_sources[0x2d]	3846	1			T3	29		T6	25		T7	12
valid_sources[0x2e]	3222	1			T3	29		T6	25		T7	19
valid_sources[0x2f]	3915	1			T3	46		T6	24		T7	14
valid_sources[0x30]	3474	1			T3	39		T6	30		T7	16
valid_sources[0x31]	4079	1			T3	39		T6	28		T7	19
valid_sources[0x32]	3185	1			T3	46		T6	34		T7	11
valid_sources[0x33]	3884	1			T3	41		T6	28		T7	12
valid_sources[0x34]	4719	1			T3	42		T6	27		T7	12
valid_sources[0x35]	5186	1			T3	28		T6	32		T7	7
valid_sources[0x36]	3800	1			T3	34		T6	31		T7	19
valid_sources[0x37]	4599	1			T3	50		T6	32		T7	17
valid_sources[0x38]	3861	1			T3	38		T6	28		T7	7
valid_sources[0x39]	5720	1			T3	37		T6	45		T7	15
valid_sources[0x3a]	3611	1			T3	34		T6	28		T7	18
valid_sources[0x3b]	7145	1			T3	42		T6	36		T7	8
valid_sources[0x3c]	3576	1			T3	36		T6	46		T7	18
valid_sources[0x3d]	3391	1			T3	39		T6	28		T7	17
valid_sources[0x3e]	3485	1			T3	27		T6	30		T7	22
valid_sources[0x3f]	5168	1			T3	58		T6	24		T7	16
valid_sources[0x40]	4189	1			T3	43		T6	39		T7	17
valid_sources[0x41]	3107	1			T3	37		T6	23		T7	12
valid_sources[0x42]	4918	1			T3	33		T6	35		T7	13
valid_sources[0x43]	4177	1			T3	36		T6	35		T7	16
valid_sources[0x44]	3742	1			T3	38		T6	32		T7	17
valid_sources[0x45]	3545	1			T3	39		T6	37		T7	17
valid_sources[0x46]	4034	1			T3	34		T6	32		T7	7
valid_sources[0x47]	4155	1			T3	50		T6	33		T7	8
valid_sources[0x48]	3846	1			T3	44		T6	36		T7	7
valid_sources[0x49]	3895	1			T3	34		T6	37		T7	7
valid_sources[0x4a]	3319	1			T3	37		T6	32		T7	10
valid_sources[0x4b]	7831	1			T3	35		T6	32		T7	11
valid_sources[0x4c]	3831	1			T3	36		T6	28		T7	7
valid_sources[0x4d]	3703	1			T3	25		T6	33		T7	18
valid_sources[0x4e]	4844	1			T3	30		T6	36		T7	9
valid_sources[0x4f]	5517	1			T3	48		T6	42		T7	13
valid_sources[0x50]	6969	1			T3	44		T6	35		T7	14
valid_sources[0x51]	3528	1			T3	46		T6	25		T7	24
valid_sources[0x52]	4446	1			T3	27		T6	38		T7	8
valid_sources[0x53]	4225	1			T3	46		T6	27		T7	15
valid_sources[0x54]	7399	1			T3	33		T6	36		T7	8
valid_sources[0x55]	3800	1			T3	39		T6	39		T7	15
valid_sources[0x56]	4591	1			T3	29		T6	44		T7	10
valid_sources[0x57]	4310	1			T3	35		T6	27		T7	6
valid_sources[0x58]	6886	1			T3	41		T6	38		T7	12
valid_sources[0x59]	3015	1			T3	42		T6	28		T7	7
valid_sources[0x5a]	3865	1			T3	56		T6	38		T7	13
valid_sources[0x5b]	4383	1			T3	37		T6	27		T7	18
valid_sources[0x5c]	3909	1			T3	39		T6	35		T7	9
valid_sources[0x5d]	3406	1			T3	27		T6	34		T7	20
valid_sources[0x5e]	3890	1			T3	40		T6	33		T7	15
valid_sources[0x5f]	4853	1			T3	26		T6	33		T7	11
valid_sources[0x60]	5369	1			T3	56		T6	43		T7	17
valid_sources[0x61]	4303	1			T3	38		T6	35		T7	6
valid_sources[0x62]	3819	1			T3	47		T6	20		T7	13
valid_sources[0x63]	3660	1			T3	49		T6	45		T7	22
valid_sources[0x64]	3679	1			T3	42		T6	32		T7	12
valid_sources[0x65]	4095	1			T3	48		T6	35		T7	12
valid_sources[0x66]	4765	1			T3	35		T6	44		T7	22
valid_sources[0x67]	3421	1			T3	34		T6	26		T7	13
valid_sources[0x68]	4673	1			T3	23		T6	37		T7	13
valid_sources[0x69]	3610	1			T3	46		T6	35		T7	9
valid_sources[0x6a]	4075	1			T3	39		T6	24		T7	11
valid_sources[0x6b]	3830	1			T3	47		T6	35		T7	17
valid_sources[0x6c]	3623	1			T3	46		T6	36		T7	11
valid_sources[0x6d]	3413	1			T3	52		T6	37		T7	9
valid_sources[0x6e]	4380	1			T3	49		T6	40		T7	11
valid_sources[0x6f]	3672	1			T3	31		T6	24		T7	21
valid_sources[0x70]	3317	1			T3	58		T6	40		T7	7
valid_sources[0x71]	3577	1			T3	36		T6	41		T7	7
valid_sources[0x72]	3122	1			T3	46		T6	29		T7	4
valid_sources[0x73]	4803	1			T3	30		T6	21		T7	14
valid_sources[0x74]	3780	1			T3	41		T6	29		T7	11
valid_sources[0x75]	4730	1			T3	44		T6	28		T7	13
valid_sources[0x76]	4657	1			T3	46		T6	35		T7	22
valid_sources[0x77]	3664	1			T3	39		T6	18		T7	14
valid_sources[0x78]	3302	1			T3	38		T6	33		T7	22
valid_sources[0x79]	3508	1			T3	31		T6	33		T7	11
valid_sources[0x7a]	4782	1			T3	31		T6	37		T7	25
valid_sources[0x7b]	3935	1			T3	21		T6	20		T7	16
valid_sources[0x7c]	3696	1			T3	27		T6	27		T7	17
valid_sources[0x7d]	4581	1			T3	40		T6	27		T7	14
valid_sources[0x7e]	3764	1			T3	41		T6	33		T7	4
valid_sources[0x7f]	3776	1			T3	49		T6	28		T7	25
valid_sources[0x80]	3851	1			T3	46		T6	29		T7	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

263426

1

T1

685

T3

2559

T4

81

values[0x0]

all_enables

biggest_size

85357

1

T1

268

T3

789

T4

37

values[0x1]

all_enables

biggest_size

45376

1

T1

131

T3

376

T4

17