Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T6,T10

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	58955745	9283	0	0
CascadeEffAonToRstPorAboveRise_A	58955745	9283	0	0
CascadeEffAonToRstPorIoAboveFall_A	56595803	9283	0	0
CascadeEffAonToRstPorIoAboveRise_A	56595803	9283	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	28298798	9283	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	28298798	9283	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	14148970	9283	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	14148970	9283	0	0
CascadeEffAonToRstPorUcbAboveFall_A	28298695	9283	0	0
CascadeEffAonToRstPorUcbAboveRise_A	28298695	9283	0	0
CascadeLcToLcAboveFall_A	58955745	23228	0	0
CascadeLcToLcAboveRise_A	58955745	23228	0	0
CascadeLcToLcAonAboveFall_A	1786406	23228	0	0
CascadeLcToLcAonAboveRise_A	1786406	23228	0	0
CascadeLcToLcShadowedAboveFall_A	58955745	23228	0	0
CascadeLcToLcShadowedAboveRise_A	58955745	23228	0	0
CascadePorToAonAboveFall_A	1786406	7243	0	0
CascadeSysToSysAboveFall_A	58955745	23228	0	0
CascadeSysToSysAboveRise_A	58955745	23228	0	0
ScanRstToAonRise_A	1786406	215	0	0
StablePorToAonRise_A	1786406	9283	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12569536	23228	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12569536	23228	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12569536	23228	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12569536	23228	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	14148970	23228	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	14148970	23228	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12569536	23228	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12569536	23228	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12569536	23228	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12569536	23228	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	9283	0	0
T1	236315	27	0	0
T2	24839	2	0	0
T3	705751	72	0	0
T4	19150	2	0	0
T5	14748	2	0	0
T6	265282	51	0	0
T7	122201	27	0	0
T8	20820	2	0	0
T9	18138	2	0	0
T10	286559	51	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	9283	0	0
T1	236315	27	0	0
T2	24839	2	0	0
T3	705751	72	0	0
T4	19150	2	0	0
T5	14748	2	0	0
T6	265282	51	0	0
T7	122201	27	0	0
T8	20820	2	0	0
T9	18138	2	0	0
T10	286559	51	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56595803	9283	0	0
T1	226864	27	0	0
T2	23845	2	0	0
T3	677562	72	0	0
T4	18376	2	0	0
T5	14160	2	0	0
T6	254654	51	0	0
T7	117269	27	0	0
T8	19986	2	0	0
T9	17415	2	0	0
T10	275069	51	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56595803	9283	0	0
T1	226864	27	0	0
T2	23845	2	0	0
T3	677562	72	0	0
T4	18376	2	0	0
T5	14160	2	0	0
T6	254654	51	0	0
T7	117269	27	0	0
T8	19986	2	0	0
T9	17415	2	0	0
T10	275069	51	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298798	9283	0	0
T1	113409	27	0	0
T2	11922	2	0	0
T3	338776	72	0	0
T4	9188	2	0	0
T5	7081	2	0	0
T6	127328	51	0	0
T7	58661	27	0	0
T8	9994	2	0	0
T9	8707	2	0	0
T10	137543	51	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298798	9283	0	0
T1	113409	27	0	0
T2	11922	2	0	0
T3	338776	72	0	0
T4	9188	2	0	0
T5	7081	2	0	0
T6	127328	51	0	0
T7	58661	27	0	0
T8	9994	2	0	0
T9	8707	2	0	0
T10	137543	51	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	9283	0	0
T1	56715	27	0	0
T2	5960	2	0	0
T3	169387	72	0	0
T4	4594	2	0	0
T5	3540	2	0	0
T6	63665	51	0	0
T7	29327	27	0	0
T8	4996	2	0	0
T9	4352	2	0	0
T10	68767	51	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	9283	0	0
T1	56715	27	0	0
T2	5960	2	0	0
T3	169387	72	0	0
T4	4594	2	0	0
T5	3540	2	0	0
T6	63665	51	0	0
T7	29327	27	0	0
T8	4996	2	0	0
T9	4352	2	0	0
T10	68767	51	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298695	9283	0	0
T1	113422	27	0	0
T2	11922	2	0	0
T3	338772	72	0	0
T4	9188	2	0	0
T5	7081	2	0	0
T6	127339	51	0	0
T7	58658	27	0	0
T8	9993	2	0	0
T9	8705	2	0	0
T10	137547	51	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298695	9283	0	0
T1	113422	27	0	0
T2	11922	2	0	0
T3	338772	72	0	0
T4	9188	2	0	0
T5	7081	2	0	0
T6	127339	51	0	0
T7	58658	27	0	0
T8	9993	2	0	0
T9	8705	2	0	0
T10	137547	51	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	23228	0	0
T1	236315	102	0	0
T2	24839	2	0	0
T3	705751	198	0	0
T4	19150	6	0	0
T5	14748	6	0	0
T6	265282	146	0	0
T7	122201	102	0	0
T8	20820	6	0	0
T9	18138	6	0	0
T10	286559	146	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	23228	0	0
T1	236315	102	0	0
T2	24839	2	0	0
T3	705751	198	0	0
T4	19150	6	0	0
T5	14748	6	0	0
T6	265282	146	0	0
T7	122201	102	0	0
T8	20820	6	0	0
T9	18138	6	0	0
T10	286559	146	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	23228	0	0
T1	7103	102	0	0
T2	745	2	0	0
T3	21421	198	0	0
T4	573	6	0	0
T5	441	6	0	0
T6	8124	146	0	0
T7	3679	102	0	0
T8	624	6	0	0
T9	543	6	0	0
T10	8705	146	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	23228	0	0
T1	7103	102	0	0
T2	745	2	0	0
T3	21421	198	0	0
T4	573	6	0	0
T5	441	6	0	0
T6	8124	146	0	0
T7	3679	102	0	0
T8	624	6	0	0
T9	543	6	0	0
T10	8705	146	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	23228	0	0
T1	236315	102	0	0
T2	24839	2	0	0
T3	705751	198	0	0
T4	19150	6	0	0
T5	14748	6	0	0
T6	265282	146	0	0
T7	122201	102	0	0
T8	20820	6	0	0
T9	18138	6	0	0
T10	286559	146	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	23228	0	0
T1	236315	102	0	0
T2	24839	2	0	0
T3	705751	198	0	0
T4	19150	6	0	0
T5	14748	6	0	0
T6	265282	146	0	0
T7	122201	102	0	0
T8	20820	6	0	0
T9	18138	6	0	0
T10	286559	146	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	7243	0	0
T1	7103	27	0	0
T2	745	21	0	0
T3	21421	40	0	0
T4	573	1	0	0
T5	441	1	0	0
T6	8124	27	0	0
T7	3679	27	0	0
T8	624	1	0	0
T9	543	1	0	0
T10	8705	23	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	23228	0	0
T1	236315	102	0	0
T2	24839	2	0	0
T3	705751	198	0	0
T4	19150	6	0	0
T5	14748	6	0	0
T6	265282	146	0	0
T7	122201	102	0	0
T8	20820	6	0	0
T9	18138	6	0	0
T10	286559	146	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58955745	23228	0	0
T1	236315	102	0	0
T2	24839	2	0	0
T3	705751	198	0	0
T4	19150	6	0	0
T5	14748	6	0	0
T6	265282	146	0	0
T7	122201	102	0	0
T8	20820	6	0	0
T9	18138	6	0	0
T10	286559	146	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	215	0	0
T3	21421	2	0	0
T4	573	0	0	0
T5	441	1	0	0
T6	8124	3	0	0
T7	3679	0	0	0
T8	624	0	0	0
T9	543	0	0	0
T10	8705	3	0	0
T20	2613	0	0	0
T30	5008	0	0	0
T31	0	1	0	0
T45	0	5	0	0
T46	0	1	0	0
T76	0	6	0	0
T88	0	1	0	0
T89	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	9283	0	0
T1	7103	27	0	0
T2	745	2	0	0
T3	21421	72	0	0
T4	573	2	0	0
T5	441	2	0	0
T6	8124	51	0	0
T7	3679	27	0	0
T8	624	2	0	0
T9	543	2	0	0
T10	8705	51	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	23228	0	0
T1	56715	102	0	0
T2	5960	2	0	0
T3	169387	198	0	0
T4	4594	6	0	0
T5	3540	6	0	0
T6	63665	146	0	0
T7	29327	102	0	0
T8	4996	6	0	0
T9	4352	6	0	0
T10	68767	146	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	23228	0	0
T1	56715	102	0	0
T2	5960	2	0	0
T3	169387	198	0	0
T4	4594	6	0	0
T5	3540	6	0	0
T6	63665	146	0	0
T7	29327	102	0	0
T8	4996	6	0	0
T9	4352	6	0	0
T10	68767	146	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12569536	23228	0	0
T1	53312	102	0	0
T2	5846	2	0	0
T3	152501	198	0	0
T4	4357	6	0	0
T5	3249	6	0	0
T6	52900	146	0	0
T7	26396	102	0	0
T8	4612	6	0	0
T9	4253	6	0	0
T10	57392	146	0	0