Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T8
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	14148970	15004	0	0
gen_assertions[0].RstEnOn_A	14148970	1260	0	0
gen_assertions[0].RstNOff_A	14148970	15004	0	0
gen_assertions[0].RstNOn_A	14148970	1260	0	0
gen_assertions[1].RstEnOff_A	56595803	13625	0	0
gen_assertions[1].RstEnOn_A	56595803	1174	0	0
gen_assertions[1].RstNOff_A	56595803	13625	0	0
gen_assertions[1].RstNOn_A	56595803	1174	0	0
gen_assertions[2].RstEnOff_A	28298798	13683	0	0
gen_assertions[2].RstEnOn_A	28298798	1174	0	0
gen_assertions[2].RstNOff_A	28298798	13683	0	0
gen_assertions[2].RstNOn_A	28298798	1174	0	0
gen_assertions[3].RstEnOff_A	28298695	13759	0	0
gen_assertions[3].RstEnOn_A	28298695	1235	0	0
gen_assertions[3].RstNOff_A	28298695	13759	0	0
gen_assertions[3].RstNOn_A	28298695	1235	0	0
gen_assertions[4].RstEnOff_A	1786406	23090	0	0
gen_assertions[4].RstEnOn_A	1786406	1255	0	0
gen_assertions[4].RstNOff_A	1786406	23090	0	0
gen_assertions[4].RstNOn_A	1786406	1255	0	0
gen_assertions[5].RstEnOff_A	14148970	15220	0	0
gen_assertions[5].RstEnOn_A	14148970	1316	0	0
gen_assertions[5].RstNOff_A	14148970	15220	0	0
gen_assertions[5].RstNOn_A	14148970	1316	0	0
gen_assertions[6].RstEnOff_A	14148970	15295	0	0
gen_assertions[6].RstEnOn_A	14148970	1386	0	0
gen_assertions[6].RstNOff_A	14148970	15295	0	0
gen_assertions[6].RstNOn_A	14148970	1386	0	0
gen_assertions[7].RstEnOff_A	14148970	15357	0	0
gen_assertions[7].RstEnOn_A	14148970	1448	0	0
gen_assertions[7].RstNOff_A	14148970	15357	0	0
gen_assertions[7].RstNOn_A	14148970	1448	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15004	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	141	0	0
T4	4594	4	0	0
T5	3540	4	0	0
T6	63665	112	0	0
T7	29327	75	0	0
T8	4996	5	0	0
T9	4352	4	0	0
T10	68767	138	0	0
T20	0	37	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1260	0	0
T3	169387	17	0	0
T4	4594	0	0	0
T5	3540	0	0	0
T6	63665	20	0	0
T7	29327	0	0	0
T8	4996	1	0	0
T9	4352	0	0	0
T10	68767	43	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	12	0	0
T32	0	6	0	0
T33	0	9	0	0
T51	0	4	0	0
T75	0	1	0	0
T76	0	11	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15004	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	141	0	0
T4	4594	4	0	0
T5	3540	4	0	0
T6	63665	112	0	0
T7	29327	75	0	0
T8	4996	5	0	0
T9	4352	4	0	0
T10	68767	138	0	0
T20	0	37	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1260	0	0
T3	169387	17	0	0
T4	4594	0	0	0
T5	3540	0	0	0
T6	63665	20	0	0
T7	29327	0	0	0
T8	4996	1	0	0
T9	4352	0	0	0
T10	68767	43	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	12	0	0
T32	0	6	0	0
T33	0	9	0	0
T51	0	4	0	0
T75	0	1	0	0
T76	0	11	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56595803	13625	0	0
T1	226864	64	0	0
T2	23845	0	0	0
T3	677562	132	0	0
T4	18376	4	0	0
T5	14160	2	0	0
T6	254654	97	0	0
T7	117269	62	0	0
T8	19986	4	0	0
T9	17415	3	0	0
T10	275069	135	0	0
T20	0	31	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56595803	1174	0	0
T3	677562	19	0	0
T4	18376	0	0	0
T5	14160	0	0	0
T6	254654	18	0	0
T7	117269	0	0	0
T8	19986	0	0	0
T9	17415	0	0	0
T10	275069	46	0	0
T20	80916	0	0	0
T30	158610	0	0	0
T31	0	13	0	0
T32	0	11	0	0
T33	0	7	0	0
T34	0	1	0	0
T51	0	6	0	0
T56	0	1	0	0
T75	0	1	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56595803	13625	0	0
T1	226864	64	0	0
T2	23845	0	0	0
T3	677562	132	0	0
T4	18376	4	0	0
T5	14160	2	0	0
T6	254654	97	0	0
T7	117269	62	0	0
T8	19986	4	0	0
T9	17415	3	0	0
T10	275069	135	0	0
T20	0	31	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56595803	1174	0	0
T3	677562	19	0	0
T4	18376	0	0	0
T5	14160	0	0	0
T6	254654	18	0	0
T7	117269	0	0	0
T8	19986	0	0	0
T9	17415	0	0	0
T10	275069	46	0	0
T20	80916	0	0	0
T30	158610	0	0	0
T31	0	13	0	0
T32	0	11	0	0
T33	0	7	0	0
T34	0	1	0	0
T51	0	6	0	0
T56	0	1	0	0
T75	0	1	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298798	13683	0	0
T1	113409	64	0	0
T2	11922	0	0	0
T3	338776	128	0	0
T4	9188	5	0	0
T5	7081	2	0	0
T6	127328	98	0	0
T7	58661	62	0	0
T8	9994	4	0	0
T9	8707	3	0	0
T10	137543	131	0	0
T20	0	31	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298798	1174	0	0
T3	338776	15	0	0
T4	9188	1	0	0
T5	7081	0	0	0
T6	127328	18	0	0
T7	58661	0	0	0
T8	9994	0	0	0
T9	8707	0	0	0
T10	137543	42	0	0
T20	40463	0	0	0
T30	79307	0	0	0
T31	0	13	0	0
T32	0	9	0	0
T33	0	9	0	0
T51	0	8	0	0
T75	0	1	0	0
T76	0	14	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298798	13683	0	0
T1	113409	64	0	0
T2	11922	0	0	0
T3	338776	128	0	0
T4	9188	5	0	0
T5	7081	2	0	0
T6	127328	98	0	0
T7	58661	62	0	0
T8	9994	4	0	0
T9	8707	3	0	0
T10	137543	131	0	0
T20	0	31	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298798	1174	0	0
T3	338776	15	0	0
T4	9188	1	0	0
T5	7081	0	0	0
T6	127328	18	0	0
T7	58661	0	0	0
T8	9994	0	0	0
T9	8707	0	0	0
T10	137543	42	0	0
T20	40463	0	0	0
T30	79307	0	0	0
T31	0	13	0	0
T32	0	9	0	0
T33	0	9	0	0
T51	0	8	0	0
T75	0	1	0	0
T76	0	14	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298695	13759	0	0
T1	113422	64	0	0
T2	11922	0	0	0
T3	338772	128	0	0
T4	9188	4	0	0
T5	7081	2	0	0
T6	127339	100	0	0
T7	58658	62	0	0
T8	9993	4	0	0
T9	8705	3	0	0
T10	137547	126	0	0
T20	0	31	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298695	1235	0	0
T3	338772	13	0	0
T4	9188	0	0	0
T5	7081	0	0	0
T6	127339	21	0	0
T7	58658	0	0	0
T8	9993	0	0	0
T9	8705	0	0	0
T10	137547	36	0	0
T20	40464	0	0	0
T30	79308	0	0	0
T31	0	12	0	0
T32	0	11	0	0
T33	0	10	0	0
T34	0	1	0	0
T51	0	8	0	0
T75	0	1	0	0
T76	0	13	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298695	13759	0	0
T1	113422	64	0	0
T2	11922	0	0	0
T3	338772	128	0	0
T4	9188	4	0	0
T5	7081	2	0	0
T6	127339	100	0	0
T7	58658	62	0	0
T8	9993	4	0	0
T9	8705	3	0	0
T10	137547	126	0	0
T20	0	31	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28298695	1235	0	0
T3	338772	13	0	0
T4	9188	0	0	0
T5	7081	0	0	0
T6	127339	21	0	0
T7	58658	0	0	0
T8	9993	0	0	0
T9	8705	0	0	0
T10	137547	36	0	0
T20	40464	0	0	0
T30	79308	0	0	0
T31	0	12	0	0
T32	0	11	0	0
T33	0	10	0	0
T34	0	1	0	0
T51	0	8	0	0
T75	0	1	0	0
T76	0	13	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	23090	0	0
T1	7103	100	0	0
T2	745	2	0	0
T3	21421	210	0	0
T4	573	6	0	0
T5	441	6	0	0
T6	8124	159	0	0
T7	3679	76	0	0
T8	624	7	0	0
T9	543	6	0	0
T10	8705	177	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	1255	0	0
T3	21421	17	0	0
T4	573	0	0	0
T5	441	0	0	0
T6	8124	20	0	0
T7	3679	0	0	0
T8	624	1	0	0
T9	543	0	0	0
T10	8705	37	0	0
T20	2613	0	0	0
T30	5008	0	0	0
T31	0	11	0	0
T32	0	11	0	0
T33	0	11	0	0
T34	0	1	0	0
T51	0	11	0	0
T56	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	23090	0	0
T1	7103	100	0	0
T2	745	2	0	0
T3	21421	210	0	0
T4	573	6	0	0
T5	441	6	0	0
T6	8124	159	0	0
T7	3679	76	0	0
T8	624	7	0	0
T9	543	6	0	0
T10	8705	177	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1786406	1255	0	0
T3	21421	17	0	0
T4	573	0	0	0
T5	441	0	0	0
T6	8124	20	0	0
T7	3679	0	0	0
T8	624	1	0	0
T9	543	0	0	0
T10	8705	37	0	0
T20	2613	0	0	0
T30	5008	0	0	0
T31	0	11	0	0
T32	0	11	0	0
T33	0	11	0	0
T34	0	1	0	0
T51	0	11	0	0
T56	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15220	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	137	0	0
T4	4594	4	0	0
T5	3540	4	0	0
T6	63665	114	0	0
T7	29327	75	0	0
T8	4996	4	0	0
T9	4352	4	0	0
T10	68767	136	0	0
T20	0	37	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1316	0	0
T3	169387	14	0	0
T4	4594	0	0	0
T5	3540	0	0	0
T6	63665	20	0	0
T7	29327	0	0	0
T8	4996	0	0	0
T9	4352	0	0	0
T10	68767	42	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	14	0	0
T32	0	14	0	0
T33	0	11	0	0
T51	0	11	0	0
T56	0	1	0	0
T76	0	11	0	0
T77	0	11	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15220	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	137	0	0
T4	4594	4	0	0
T5	3540	4	0	0
T6	63665	114	0	0
T7	29327	75	0	0
T8	4996	4	0	0
T9	4352	4	0	0
T10	68767	136	0	0
T20	0	37	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1316	0	0
T3	169387	14	0	0
T4	4594	0	0	0
T5	3540	0	0	0
T6	63665	20	0	0
T7	29327	0	0	0
T8	4996	0	0	0
T9	4352	0	0	0
T10	68767	42	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	14	0	0
T32	0	14	0	0
T33	0	11	0	0
T51	0	11	0	0
T56	0	1	0	0
T76	0	11	0	0
T77	0	11	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15295	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	136	0	0
T4	4594	4	0	0
T5	3540	4	0	0
T6	63665	114	0	0
T7	29327	75	0	0
T8	4996	4	0	0
T9	4352	4	0	0
T10	68767	134	0	0
T20	0	37	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1386	0	0
T3	169387	11	0	0
T4	4594	0	0	0
T5	3540	0	0	0
T6	63665	21	0	0
T7	29327	0	0	0
T8	4996	0	0	0
T9	4352	0	0	0
T10	68767	39	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	11	0	0
T32	0	15	0	0
T33	0	12	0	0
T51	0	12	0	0
T76	0	11	0	0
T77	0	12	0	0
T78	0	6	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15295	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	136	0	0
T4	4594	4	0	0
T5	3540	4	0	0
T6	63665	114	0	0
T7	29327	75	0	0
T8	4996	4	0	0
T9	4352	4	0	0
T10	68767	134	0	0
T20	0	37	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1386	0	0
T3	169387	11	0	0
T4	4594	0	0	0
T5	3540	0	0	0
T6	63665	21	0	0
T7	29327	0	0	0
T8	4996	0	0	0
T9	4352	0	0	0
T10	68767	39	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	11	0	0
T32	0	15	0	0
T33	0	12	0	0
T51	0	12	0	0
T76	0	11	0	0
T77	0	12	0	0
T78	0	6	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15357	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	140	0	0
T4	4594	5	0	0
T5	3540	4	0	0
T6	63665	119	0	0
T7	29327	75	0	0
T8	4996	5	0	0
T9	4352	4	0	0
T10	68767	144	0	0
T20	0	37	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1448	0	0
T3	169387	15	0	0
T4	4594	1	0	0
T5	3540	0	0	0
T6	63665	27	0	0
T7	29327	0	0	0
T8	4996	1	0	0
T9	4352	0	0	0
T10	68767	49	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	10	0	0
T32	0	15	0	0
T33	0	14	0	0
T34	0	1	0	0
T51	0	12	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	15357	0	0
T1	56715	75	0	0
T2	5960	0	0	0
T3	169387	140	0	0
T4	4594	5	0	0
T5	3540	4	0	0
T6	63665	119	0	0
T7	29327	75	0	0
T8	4996	5	0	0
T9	4352	4	0	0
T10	68767	144	0	0
T20	0	37	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14148970	1448	0	0
T3	169387	15	0	0
T4	4594	1	0	0
T5	3540	0	0	0
T6	63665	27	0	0
T7	29327	0	0	0
T8	4996	1	0	0
T9	4352	0	0	0
T10	68767	49	0	0
T20	20229	0	0	0
T30	39649	0	0	0
T31	0	10	0	0
T32	0	15	0	0
T33	0	14	0	0
T34	0	1	0	0
T51	0	12	0	0