Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13350986	9043	0	0
alert_regwen_rd_A	13350986	5958	0	0
cpu_regwen_rd_A	13350986	6226	0	0
sw_rst_ctrl_n_0_rd_A	13350986	13421	0	0
sw_rst_ctrl_n_1_rd_A	13350986	13966	0	0
sw_rst_ctrl_n_2_rd_A	13350986	13868	0	0
sw_rst_ctrl_n_3_rd_A	13350986	13628	0	0
sw_rst_ctrl_n_4_rd_A	13350986	13793	0	0
sw_rst_ctrl_n_5_rd_A	13350986	13572	0	0
sw_rst_ctrl_n_6_rd_A	13350986	14050	0	0
sw_rst_ctrl_n_7_rd_A	13350986	13580	0	0
sw_rst_regwen_0_rd_A	13350986	7082	0	0
sw_rst_regwen_1_rd_A	13350986	6879	0	0
sw_rst_regwen_2_rd_A	13350986	6979	0	0
sw_rst_regwen_3_rd_A	13350986	7017	0	0
sw_rst_regwen_4_rd_A	13350986	6927	0	0
sw_rst_regwen_5_rd_A	13350986	6608	0	0
sw_rst_regwen_6_rd_A	13350986	6868	0	0
sw_rst_regwen_7_rd_A	13350986	7103	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	9043	0	0
T52	17670	1	0	0
T53	3073	22	0	0
T55	21844	2	0	0
T57	3744	147	0	0
T58	8526	556	0	0
T79	10741	696	0	0
T80	5275	441	0	0
T81	13108	522	0	0
T82	3709	104	0	0
T83	3894	46	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	5958	0	0
T3	152501	216	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	32	0	0
T76	0	170	0	0
T89	0	243	0	0
T90	0	13	0	0
T91	0	290	0	0
T111	0	46	0	0
T112	0	326	0	0
T113	0	83	0	0
T114	0	159	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	6226	0	0
T3	152501	238	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	39	0	0
T76	0	195	0	0
T89	0	263	0	0
T90	0	26	0	0
T91	0	278	0	0
T111	0	70	0	0
T112	0	357	0	0
T113	0	89	0	0
T114	0	157	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	13421	0	0
T3	152501	408	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	50	0	0
T76	0	315	0	0
T77	0	165	0	0
T89	0	522	0	0
T90	0	48	0	0
T115	0	66	0	0
T116	0	228	0	0
T117	0	128	0	0
T118	0	71	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	13966	0	0
T3	152501	396	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	33	0	0
T76	0	336	0	0
T77	0	186	0	0
T89	0	568	0	0
T90	0	32	0	0
T115	0	61	0	0
T116	0	210	0	0
T117	0	140	0	0
T118	0	77	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	13868	0	0
T3	152501	425	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	41	0	0
T76	0	342	0	0
T77	0	188	0	0
T89	0	535	0	0
T90	0	56	0	0
T115	0	59	0	0
T116	0	199	0	0
T117	0	123	0	0
T118	0	72	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	13628	0	0
T3	152501	392	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	17	0	0
T76	0	287	0	0
T77	0	212	0	0
T89	0	537	0	0
T90	0	21	0	0
T115	0	66	0	0
T116	0	220	0	0
T117	0	149	0	0
T118	0	56	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	13793	0	0
T3	152501	363	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	38	0	0
T76	0	383	0	0
T77	0	202	0	0
T89	0	515	0	0
T90	0	39	0	0
T115	0	63	0	0
T116	0	174	0	0
T117	0	127	0	0
T118	0	62	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	13572	0	0
T3	152501	387	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	49	0	0
T76	0	318	0	0
T77	0	191	0	0
T89	0	545	0	0
T90	0	44	0	0
T115	0	67	0	0
T116	0	217	0	0
T117	0	139	0	0
T118	0	55	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	14050	0	0
T3	152501	417	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	14	0	0
T76	0	349	0	0
T77	0	211	0	0
T89	0	554	0	0
T90	0	41	0	0
T115	0	50	0	0
T116	0	186	0	0
T117	0	140	0	0
T118	0	67	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	13580	0	0
T3	152501	436	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	50	0	0
T76	0	327	0	0
T77	0	186	0	0
T89	0	538	0	0
T90	0	30	0	0
T115	0	51	0	0
T116	0	221	0	0
T117	0	131	0	0
T118	0	46	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	7082	0	0
T3	152501	222	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	46	0	0
T76	0	176	0	0
T77	0	29	0	0
T89	0	236	0	0
T90	0	15	0	0
T91	0	254	0	0
T116	0	34	0	0
T117	0	44	0	0
T119	0	30	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	6879	0	0
T3	152501	218	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	42	0	0
T76	0	151	0	0
T77	0	47	0	0
T89	0	258	0	0
T90	0	28	0	0
T91	0	210	0	0
T116	0	29	0	0
T117	0	15	0	0
T119	0	37	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	6979	0	0
T3	152501	162	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	43	0	0
T76	0	221	0	0
T77	0	26	0	0
T89	0	254	0	0
T90	0	40	0	0
T91	0	265	0	0
T116	0	23	0	0
T117	0	27	0	0
T119	0	28	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	7017	0	0
T3	152501	200	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	33	0	0
T76	0	218	0	0
T77	0	30	0	0
T89	0	226	0	0
T90	0	39	0	0
T91	0	247	0	0
T116	0	34	0	0
T117	0	26	0	0
T119	0	32	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	6927	0	0
T3	152501	212	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	41	0	0
T76	0	254	0	0
T77	0	18	0	0
T89	0	201	0	0
T90	0	41	0	0
T91	0	279	0	0
T116	0	22	0	0
T117	0	20	0	0
T119	0	30	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	6608	0	0
T3	152501	194	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	22	0	0
T76	0	182	0	0
T77	0	14	0	0
T89	0	271	0	0
T90	0	40	0	0
T91	0	250	0	0
T116	0	15	0	0
T117	0	27	0	0
T119	0	33	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	6868	0	0
T3	152501	209	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	27	0	0
T76	0	187	0	0
T77	0	30	0	0
T89	0	217	0	0
T90	0	35	0	0
T91	0	260	0	0
T116	0	56	0	0
T117	0	29	0	0
T119	0	22	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13350986	7103	0	0
T3	152501	258	0	0
T4	4357	0	0	0
T5	3249	0	0	0
T6	52900	0	0	0
T7	26396	0	0	0
T8	4612	0	0	0
T9	4253	0	0	0
T10	57392	0	0	0
T20	15802	0	0	0
T30	34668	57	0	0
T76	0	214	0	0
T77	0	31	0	0
T89	0	273	0	0
T90	0	37	0	0
T91	0	274	0	0
T116	0	25	0	0
T117	0	42	0	0
T119	0	31	0	0