Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	675495	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

406867

1

T2

72

T3

124

T4

1146

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	579323	1			T1	1		T2	99		T3	186
values[0x0]	251699	1			T2	55		T3	93		T4	626
values[0x1]	251340	1			T2	58		T3	100		T4	644

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	567195	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

515167

1

T2

93

T3

160

T4

1445

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4142	1			T7	14		T11	117		T12	27
valid_sources[0x01]	4069	1			T4	6		T7	13		T11	86
valid_sources[0x02]	4261	1			T4	17		T6	10		T7	7
valid_sources[0x03]	4120	1			T6	2		T7	21		T11	102
valid_sources[0x04]	3470	1			T4	33		T6	2		T7	21
valid_sources[0x05]	3681	1			T3	54		T6	5		T7	10
valid_sources[0x06]	3369	1			T6	5		T7	17		T11	111
valid_sources[0x07]	5920	1			T4	35		T7	2		T11	90
valid_sources[0x08]	5368	1			T4	13		T6	1		T7	12
valid_sources[0x09]	3803	1			T7	14		T10	4		T11	78
valid_sources[0x0a]	3533	1			T6	1		T7	15		T10	2
valid_sources[0x0b]	3396	1			T4	10		T6	7		T7	11
valid_sources[0x0c]	4681	1			T4	105		T6	9		T7	20
valid_sources[0x0d]	3790	1			T4	3		T7	8		T11	97
valid_sources[0x0e]	5044	1			T4	42		T7	29		T11	94
valid_sources[0x0f]	4491	1			T7	12		T11	65		T12	45
valid_sources[0x10]	5462	1			T4	4		T6	3		T7	4
valid_sources[0x11]	3579	1			T4	10		T6	2		T7	18
valid_sources[0x12]	3525	1			T6	4		T7	6		T11	70
valid_sources[0x13]	5037	1			T7	17		T10	3		T11	68
valid_sources[0x14]	3541	1			T3	19		T4	1		T7	12
valid_sources[0x15]	4830	1			T4	38		T7	15		T10	1
valid_sources[0x16]	4306	1			T4	3		T6	1		T7	14
valid_sources[0x17]	3681	1			T6	9		T7	31		T10	1
valid_sources[0x18]	3697	1			T7	16		T11	104		T12	45
valid_sources[0x19]	4020	1			T4	24		T6	6		T7	7
valid_sources[0x1a]	4469	1			T6	1		T7	26		T11	68
valid_sources[0x1b]	3911	1			T7	32		T11	101		T12	40
valid_sources[0x1c]	4623	1			T6	1		T7	13		T11	89
valid_sources[0x1d]	6162	1			T6	4		T7	14		T10	3
valid_sources[0x1e]	4181	1			T3	27		T4	56		T7	40
valid_sources[0x1f]	4734	1			T6	3		T7	3		T11	101
valid_sources[0x20]	4637	1			T4	1		T6	1		T7	3
valid_sources[0x21]	3804	1			T4	15		T7	2		T11	113
valid_sources[0x22]	3923	1			T6	6		T7	18		T11	72
valid_sources[0x23]	3734	1			T4	18		T6	1		T7	6
valid_sources[0x24]	3782	1			T6	4		T7	25		T11	102
valid_sources[0x25]	4666	1			T6	6		T7	1		T24	1
valid_sources[0x26]	3374	1			T6	1		T7	9		T11	93
valid_sources[0x27]	4254	1			T4	21		T6	1		T7	13
valid_sources[0x28]	3753	1			T6	6		T7	33		T10	2
valid_sources[0x29]	5609	1			T6	2		T7	23		T10	9
valid_sources[0x2a]	4431	1			T4	63		T6	6		T7	12
valid_sources[0x2b]	3305	1			T6	3		T7	15		T11	80
valid_sources[0x2c]	3440	1			T3	32		T6	1		T7	13
valid_sources[0x2d]	3547	1			T4	4		T6	2		T7	17
valid_sources[0x2e]	3845	1			T4	17		T6	4		T7	6
valid_sources[0x2f]	4449	1			T6	6		T7	24		T11	107
valid_sources[0x30]	4880	1			T4	13		T6	13		T7	22
valid_sources[0x31]	4314	1			T6	3		T7	14		T11	48
valid_sources[0x32]	3725	1			T6	1		T7	10		T11	75
valid_sources[0x33]	3757	1			T4	28		T6	1		T7	20
valid_sources[0x34]	4587	1			T3	4		T4	4		T6	6
valid_sources[0x35]	3720	1			T4	5		T6	10		T7	19
valid_sources[0x36]	3564	1			T4	4		T6	4		T7	10
valid_sources[0x37]	3930	1			T4	19		T6	10		T7	1
valid_sources[0x38]	3783	1			T4	2		T10	2		T11	73
valid_sources[0x39]	5045	1			T7	22		T11	110		T12	44
valid_sources[0x3a]	6065	1			T6	6		T7	20		T11	97
valid_sources[0x3b]	6670	1			T4	3		T7	6		T11	103
valid_sources[0x3c]	3773	1			T7	2		T10	4		T11	77
valid_sources[0x3d]	3416	1			T7	13		T11	77		T12	50
valid_sources[0x3e]	4099	1			T4	1		T6	2		T7	13
valid_sources[0x3f]	4625	1			T1	1		T4	3		T6	6
valid_sources[0x40]	5040	1			T4	3		T6	1		T7	25
valid_sources[0x41]	6225	1			T6	11		T7	27		T11	85
valid_sources[0x42]	3345	1			T7	8		T11	65		T12	46
valid_sources[0x43]	3415	1			T6	2		T7	8		T11	95
valid_sources[0x44]	3355	1			T6	2		T7	15		T11	95
valid_sources[0x45]	3792	1			T4	9		T6	3		T7	9
valid_sources[0x46]	3723	1			T7	21		T11	63		T12	41
valid_sources[0x47]	3603	1			T4	20		T6	3		T7	7
valid_sources[0x48]	4020	1			T4	29		T6	4		T7	7
valid_sources[0x49]	4353	1			T4	36		T6	2		T7	21
valid_sources[0x4a]	3973	1			T3	32		T4	31		T6	3
valid_sources[0x4b]	3562	1			T7	19		T10	1		T11	62
valid_sources[0x4c]	4954	1			T7	3		T10	1		T11	113
valid_sources[0x4d]	3378	1			T4	48		T6	3		T7	24
valid_sources[0x4e]	3532	1			T6	6		T7	42		T11	87
valid_sources[0x4f]	4315	1			T7	11		T11	87		T12	45
valid_sources[0x50]	3851	1			T7	24		T11	93		T12	52
valid_sources[0x51]	3584	1			T6	2		T7	14		T10	4
valid_sources[0x52]	3386	1			T4	8		T7	5		T11	100
valid_sources[0x53]	4069	1			T7	2		T10	1		T11	97
valid_sources[0x54]	4068	1			T3	1		T7	5		T11	105
valid_sources[0x55]	3512	1			T6	1		T7	10		T24	1
valid_sources[0x56]	4798	1			T7	26		T47	10		T11	74
valid_sources[0x57]	9841	1			T6	5		T7	20		T10	1
valid_sources[0x58]	4536	1			T6	1		T7	13		T11	55
valid_sources[0x59]	3320	1			T3	17		T6	4		T7	16
valid_sources[0x5a]	6896	1			T4	22		T7	8		T11	81
valid_sources[0x5b]	4197	1			T4	6		T7	21		T11	110
valid_sources[0x5c]	4385	1			T7	10		T10	1		T11	85
valid_sources[0x5d]	3210	1			T6	2		T7	17		T11	108
valid_sources[0x5e]	3584	1			T4	32		T6	2		T7	12
valid_sources[0x5f]	3862	1			T6	3		T7	4		T10	1
valid_sources[0x60]	3355	1			T7	33		T10	1		T24	1
valid_sources[0x61]	5321	1			T6	1		T7	5		T11	85
valid_sources[0x62]	4012	1			T6	11		T7	10		T11	93
valid_sources[0x63]	4140	1			T4	21		T7	23		T11	73
valid_sources[0x64]	4660	1			T4	13		T6	7		T7	8
valid_sources[0x65]	3391	1			T4	46		T6	3		T7	34
valid_sources[0x66]	3494	1			T4	91		T7	17		T10	6
valid_sources[0x67]	3814	1			T4	70		T6	2		T7	13
valid_sources[0x68]	3812	1			T6	1		T7	2		T11	76
valid_sources[0x69]	5782	1			T4	2		T7	23		T11	102
valid_sources[0x6a]	3724	1			T6	18		T7	23		T11	100
valid_sources[0x6b]	3755	1			T4	11		T6	17		T7	2
valid_sources[0x6c]	4274	1			T4	18		T6	4		T7	16
valid_sources[0x6d]	6057	1			T7	5		T10	3		T11	84
valid_sources[0x6e]	5686	1			T6	7		T7	16		T11	73
valid_sources[0x6f]	3482	1			T4	82		T6	1		T7	13
valid_sources[0x70]	3661	1			T4	1		T6	1		T7	32
valid_sources[0x71]	4465	1			T3	35		T6	3		T7	24
valid_sources[0x72]	3387	1			T4	12		T6	1		T7	28
valid_sources[0x73]	3861	1			T4	12		T6	1		T7	12
valid_sources[0x74]	3552	1			T7	33		T11	74		T12	53
valid_sources[0x75]	3119	1			T4	14		T7	25		T10	8
valid_sources[0x76]	4137	1			T4	2		T6	13		T7	12
valid_sources[0x77]	3965	1			T7	6		T11	106		T12	48
valid_sources[0x78]	7450	1			T7	50		T11	90		T12	46
valid_sources[0x79]	6524	1			T6	3		T7	11		T10	1
valid_sources[0x7a]	4092	1			T4	5		T6	5		T7	11
valid_sources[0x7b]	3645	1			T4	27		T6	6		T7	2
valid_sources[0x7c]	4201	1			T6	4		T7	9		T10	4
valid_sources[0x7d]	3828	1			T4	5		T7	22		T10	4
valid_sources[0x7e]	3773	1			T6	7		T7	17		T11	70
valid_sources[0x7f]	6756	1			T4	16		T6	4		T7	22
valid_sources[0x80]	6023	1			T6	8		T7	15		T11	96

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

271608

1

T2

40

T3

77

T4

819

values[0x0]

all_enables

biggest_size

88352

1

T2

20

T3

28

T4

220

values[0x1]

all_enables

biggest_size

46907

1

T2

12

T3

19

T4

107