Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	628232	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

378005

1

T1

1099

T2

128

T3

2986

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	535970	1			T1	1500		T2	186		T3	4441
values[0x0]	235098	1			T1	854		T2	96		T3	1767
values[0x1]	235169	1			T1	846		T2	97		T3	1755

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	527605	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

478632

1

T1

1404

T2

172

T3

3814

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4024	1			T1	21		T2	3		T3	24
valid_sources[0x01]	3554	1			T1	14		T2	2		T3	26
valid_sources[0x02]	3212	1			T1	10		T2	2		T3	35
valid_sources[0x03]	4282	1			T1	12		T2	1		T3	20
valid_sources[0x04]	3561	1			T1	16		T2	1		T3	21
valid_sources[0x05]	4362	1			T1	12		T2	1		T3	5
valid_sources[0x06]	3531	1			T1	18		T3	77		T6	2
valid_sources[0x07]	3894	1			T1	13		T2	2		T3	30
valid_sources[0x08]	4605	1			T1	12		T2	3		T3	29
valid_sources[0x09]	3499	1			T1	19		T2	3		T3	20
valid_sources[0x0a]	3992	1			T1	16		T3	24		T6	5
valid_sources[0x0b]	3734	1			T1	17		T2	1		T3	19
valid_sources[0x0c]	3796	1			T1	16		T2	1		T3	76
valid_sources[0x0d]	3876	1			T1	15		T2	2		T3	26
valid_sources[0x0e]	3553	1			T1	9		T2	3		T3	53
valid_sources[0x0f]	4145	1			T1	6		T2	1		T3	23
valid_sources[0x10]	3667	1			T1	9		T3	23		T6	5
valid_sources[0x11]	7754	1			T1	9		T3	49		T4	1
valid_sources[0x12]	6898	1			T1	20		T2	1		T3	22
valid_sources[0x13]	3779	1			T1	11		T3	26		T4	1
valid_sources[0x14]	3302	1			T1	17		T2	1		T3	39
valid_sources[0x15]	4523	1			T1	15		T2	3		T3	25
valid_sources[0x16]	3692	1			T1	10		T3	37		T8	28
valid_sources[0x17]	3157	1			T1	8		T2	3		T3	31
valid_sources[0x18]	3247	1			T1	13		T2	2		T3	18
valid_sources[0x19]	3211	1			T1	6		T3	37		T4	2
valid_sources[0x1a]	5071	1			T1	6		T2	4		T3	42
valid_sources[0x1b]	4103	1			T1	18		T2	1		T3	36
valid_sources[0x1c]	3391	1			T1	13		T2	1		T3	64
valid_sources[0x1d]	6994	1			T1	7		T3	40		T4	1
valid_sources[0x1e]	3248	1			T1	5		T2	2		T3	37
valid_sources[0x1f]	3261	1			T1	5		T2	1		T3	25
valid_sources[0x20]	4640	1			T1	19		T2	2		T3	51
valid_sources[0x21]	3689	1			T1	19		T2	4		T3	30
valid_sources[0x22]	2974	1			T1	13		T3	2		T6	5
valid_sources[0x23]	3833	1			T1	21		T2	3		T3	18
valid_sources[0x24]	3186	1			T1	11		T3	13		T4	5
valid_sources[0x25]	4427	1			T1	10		T2	3		T3	12
valid_sources[0x26]	4041	1			T1	22		T3	30		T8	32
valid_sources[0x27]	3327	1			T1	19		T2	1		T3	37
valid_sources[0x28]	4157	1			T1	6		T2	1		T3	33
valid_sources[0x29]	5208	1			T1	12		T2	2		T3	59
valid_sources[0x2a]	3829	1			T1	12		T2	1		T3	55
valid_sources[0x2b]	4688	1			T1	15		T2	2		T3	18
valid_sources[0x2c]	3577	1			T1	18		T3	32		T4	1
valid_sources[0x2d]	3715	1			T1	5		T3	20		T6	4
valid_sources[0x2e]	2960	1			T1	17		T2	3		T3	15
valid_sources[0x2f]	3236	1			T1	6		T2	3		T3	40
valid_sources[0x30]	7742	1			T1	19		T2	2		T3	15
valid_sources[0x31]	3476	1			T1	10		T2	1		T3	40
valid_sources[0x32]	3707	1			T1	8		T2	2		T3	18
valid_sources[0x33]	4290	1			T1	4		T2	2		T3	14
valid_sources[0x34]	3844	1			T1	9		T2	1		T3	47
valid_sources[0x35]	3339	1			T1	15		T2	2		T3	22
valid_sources[0x36]	3042	1			T1	14		T2	4		T3	10
valid_sources[0x37]	3466	1			T1	16		T2	2		T3	11
valid_sources[0x38]	3444	1			T1	15		T2	1		T3	26
valid_sources[0x39]	3747	1			T1	8		T2	1		T3	21
valid_sources[0x3a]	3417	1			T1	16		T2	1		T3	46
valid_sources[0x3b]	3773	1			T1	5		T3	13		T6	2
valid_sources[0x3c]	3509	1			T1	11		T3	24		T6	4
valid_sources[0x3d]	3196	1			T1	19		T2	2		T3	74
valid_sources[0x3e]	4091	1			T1	17		T2	2		T3	28
valid_sources[0x3f]	2996	1			T1	12		T2	1		T3	14
valid_sources[0x40]	3708	1			T1	8		T2	2		T3	8
valid_sources[0x41]	3220	1			T1	15		T3	12		T4	2
valid_sources[0x42]	3301	1			T1	15		T2	2		T3	18
valid_sources[0x43]	3135	1			T1	9		T2	1		T3	41
valid_sources[0x44]	3317	1			T1	8		T2	2		T3	51
valid_sources[0x45]	3274	1			T1	6		T3	39		T6	6
valid_sources[0x46]	6158	1			T1	11		T3	15		T4	2
valid_sources[0x47]	3470	1			T1	18		T2	1		T3	2
valid_sources[0x48]	2884	1			T1	21		T2	5		T3	36
valid_sources[0x49]	3318	1			T1	13		T2	3		T3	30
valid_sources[0x4a]	3496	1			T1	5		T2	1		T3	42
valid_sources[0x4b]	3565	1			T1	10		T2	2		T3	46
valid_sources[0x4c]	3337	1			T1	19		T2	1		T3	44
valid_sources[0x4d]	3689	1			T1	13		T2	2		T3	51
valid_sources[0x4e]	4131	1			T1	9		T2	1		T3	43
valid_sources[0x4f]	3333	1			T1	14		T2	1		T3	21
valid_sources[0x50]	3644	1			T1	8		T2	2		T3	21
valid_sources[0x51]	3295	1			T1	15		T2	1		T3	44
valid_sources[0x52]	4893	1			T1	14		T3	9		T4	5
valid_sources[0x53]	3374	1			T1	13		T2	1		T3	28
valid_sources[0x54]	3992	1			T1	17		T2	4		T3	22
valid_sources[0x55]	3411	1			T1	13		T2	2		T3	18
valid_sources[0x56]	3414	1			T1	17		T3	13		T6	3
valid_sources[0x57]	4420	1			T1	8		T2	3		T3	46
valid_sources[0x58]	3600	1			T1	24		T3	17		T6	3
valid_sources[0x59]	3709	1			T1	11		T2	2		T3	18
valid_sources[0x5a]	3714	1			T1	13		T2	3		T3	36
valid_sources[0x5b]	3604	1			T1	1		T2	4		T3	31
valid_sources[0x5c]	3261	1			T1	7		T3	60		T4	6
valid_sources[0x5d]	3478	1			T1	13		T2	1		T3	46
valid_sources[0x5e]	3242	1			T1	13		T2	1		T3	13
valid_sources[0x5f]	6202	1			T1	2		T2	2		T3	22
valid_sources[0x60]	3620	1			T1	8		T2	2		T3	41
valid_sources[0x61]	3649	1			T1	12		T2	5		T3	7
valid_sources[0x62]	3182	1			T2	1		T3	16		T6	4
valid_sources[0x63]	3083	1			T1	14		T2	1		T3	12
valid_sources[0x64]	3562	1			T1	17		T2	3		T3	64
valid_sources[0x65]	4226	1			T1	19		T2	1		T3	31
valid_sources[0x66]	3663	1			T1	13		T3	39		T4	4
valid_sources[0x67]	3319	1			T1	14		T2	2		T3	24
valid_sources[0x68]	3322	1			T1	12		T3	53		T4	2
valid_sources[0x69]	3215	1			T1	12		T3	11		T4	11
valid_sources[0x6a]	4033	1			T1	16		T3	28		T6	3
valid_sources[0x6b]	3778	1			T1	10		T2	3		T3	38
valid_sources[0x6c]	3589	1			T1	9		T2	3		T3	25
valid_sources[0x6d]	2989	1			T1	11		T2	1		T3	40
valid_sources[0x6e]	3892	1			T1	13		T2	1		T3	13
valid_sources[0x6f]	3877	1			T1	10		T3	8		T6	7
valid_sources[0x70]	4105	1			T1	11		T2	2		T3	19
valid_sources[0x71]	8347	1			T1	16		T2	2		T3	21
valid_sources[0x72]	3837	1			T1	21		T3	36		T6	5
valid_sources[0x73]	3510	1			T1	21		T3	56		T6	7
valid_sources[0x74]	3315	1			T1	7		T2	3		T3	35
valid_sources[0x75]	3656	1			T1	19		T3	33		T6	1
valid_sources[0x76]	6197	1			T1	9		T3	27		T6	3
valid_sources[0x77]	3231	1			T1	12		T2	4		T3	26
valid_sources[0x78]	4086	1			T1	5		T3	62		T6	5
valid_sources[0x79]	3490	1			T1	8		T2	3		T3	34
valid_sources[0x7a]	3879	1			T1	12		T2	2		T3	44
valid_sources[0x7b]	3767	1			T1	15		T2	4		T3	45
valid_sources[0x7c]	3162	1			T1	10		T2	3		T3	3
valid_sources[0x7d]	3821	1			T1	13		T3	29		T6	1
valid_sources[0x7e]	3065	1			T1	4		T2	3		T3	63
valid_sources[0x7f]	3733	1			T1	5		T3	24		T6	3
valid_sources[0x80]	3696	1			T1	11		T2	1		T3	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

251651

1

T1

705

T2

77

T3

2108

values[0x0]

all_enables

biggest_size

82366

1

T1

278

T2

38

T3

601

values[0x1]

all_enables

biggest_size

43988

1

T1

116

T2

13

T3

277