Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
1	0	Covered	T3,T9,T13

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T2,T3,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54709315	8683	0	0
CascadeEffAonToRstPorAboveRise_A	54709315	8683	0	0
CascadeEffAonToRstPorIoAboveFall_A	52519633	8683	0	0
CascadeEffAonToRstPorIoAboveRise_A	52519633	8683	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26260532	8683	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26260532	8683	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13130101	8683	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13130101	8683	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26260581	8683	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26260581	8683	0	0
CascadeLcToLcAboveFall_A	54709315	22187	0	0
CascadeLcToLcAboveRise_A	54709315	22187	0	0
CascadeLcToLcAonAboveFall_A	1658844	22187	0	0
CascadeLcToLcAonAboveRise_A	1658844	22187	0	0
CascadeLcToLcShadowedAboveFall_A	54709315	22187	0	0
CascadeLcToLcShadowedAboveRise_A	54709315	22187	0	0
CascadePorToAonAboveFall_A	1658844	6918	0	0
CascadeSysToSysAboveFall_A	54709315	22187	0	0
CascadeSysToSysAboveRise_A	54709315	22187	0	0
ScanRstToAonRise_A	1658844	228	0	0
StablePorToAonRise_A	1658844	8683	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11624004	22187	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11624004	22187	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11624004	22187	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11624004	22187	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13130101	22187	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13130101	22187	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11624004	22187	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11624004	22187	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11624004	22187	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11624004	22187	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	8683	0	0
T1	235258	27	0	0
T2	11889	2	0	0
T3	422300	54	0	0
T4	17151	1	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	27	0	0
T9	107303	25	0	0
T10	24410	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	8683	0	0
T1	235258	27	0	0
T2	11889	2	0	0
T3	422300	54	0	0
T4	17151	1	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	27	0	0
T9	107303	25	0	0
T10	24410	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52519633	8683	0	0
T1	225850	27	0	0
T2	11415	2	0	0
T3	405421	54	0	0
T4	16464	1	0	0
T5	18733	2	0	0
T6	28409	1	0	0
T7	23259	8	0	0
T8	181047	27	0	0
T9	103005	25	0	0
T10	23432	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52519633	8683	0	0
T1	225850	27	0	0
T2	11415	2	0	0
T3	405421	54	0	0
T4	16464	1	0	0
T5	18733	2	0	0
T6	28409	1	0	0
T7	23259	8	0	0
T8	181047	27	0	0
T9	103005	25	0	0
T10	23432	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260532	8683	0	0
T1	112939	27	0	0
T2	5705	2	0	0
T3	202709	54	0	0
T4	8231	1	0	0
T5	9365	2	0	0
T6	14205	1	0	0
T7	11618	8	0	0
T8	90536	27	0	0
T9	51510	25	0	0
T10	11707	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260532	8683	0	0
T1	112939	27	0	0
T2	5705	2	0	0
T3	202709	54	0	0
T4	8231	1	0	0
T5	9365	2	0	0
T6	14205	1	0	0
T7	11618	8	0	0
T8	90536	27	0	0
T9	51510	25	0	0
T10	11707	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	8683	0	0
T1	56463	27	0	0
T2	2851	2	0	0
T3	101363	54	0	0
T4	4115	1	0	0
T5	4682	2	0	0
T6	7102	1	0	0
T7	5812	8	0	0
T8	45270	27	0	0
T9	25758	25	0	0
T10	5857	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	8683	0	0
T1	56463	27	0	0
T2	2851	2	0	0
T3	101363	54	0	0
T4	4115	1	0	0
T5	4682	2	0	0
T6	7102	1	0	0
T7	5812	8	0	0
T8	45270	27	0	0
T9	25758	25	0	0
T10	5857	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260581	8683	0	0
T1	112938	27	0	0
T2	5708	2	0	0
T3	202715	54	0	0
T4	8232	1	0	0
T5	9366	2	0	0
T6	14206	1	0	0
T7	11617	8	0	0
T8	90543	27	0	0
T9	51516	25	0	0
T10	11715	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260581	8683	0	0
T1	112938	27	0	0
T2	5708	2	0	0
T3	202715	54	0	0
T4	8232	1	0	0
T5	9366	2	0	0
T6	14206	1	0	0
T7	11617	8	0	0
T8	90543	27	0	0
T9	51516	25	0	0
T10	11715	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	22187	0	0
T1	235258	102	0	0
T2	11889	6	0	0
T3	422300	156	0	0
T4	17151	21	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	102	0	0
T9	107303	58	0	0
T10	24410	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	22187	0	0
T1	235258	102	0	0
T2	11889	6	0	0
T3	422300	156	0	0
T4	17151	21	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	102	0	0
T9	107303	58	0	0
T10	24410	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	22187	0	0
T1	7072	102	0	0
T2	355	6	0	0
T3	12864	156	0	0
T4	512	21	0	0
T5	584	2	0	0
T6	886	1	0	0
T7	728	8	0	0
T8	5672	102	0	0
T9	3310	58	0	0
T10	733	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	22187	0	0
T1	7072	102	0	0
T2	355	6	0	0
T3	12864	156	0	0
T4	512	21	0	0
T5	584	2	0	0
T6	886	1	0	0
T7	728	8	0	0
T8	5672	102	0	0
T9	3310	58	0	0
T10	733	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	22187	0	0
T1	235258	102	0	0
T2	11889	6	0	0
T3	422300	156	0	0
T4	17151	21	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	102	0	0
T9	107303	58	0	0
T10	24410	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	22187	0	0
T1	235258	102	0	0
T2	11889	6	0	0
T3	422300	156	0	0
T4	17151	21	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	102	0	0
T9	107303	58	0	0
T10	24410	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	6918	0	0
T1	7072	27	0	0
T2	355	1	0	0
T3	12864	29	0	0
T4	512	1	0	0
T5	584	18	0	0
T6	886	1	0	0
T7	728	8	0	0
T8	5672	27	0	0
T9	3310	16	0	0
T10	733	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	22187	0	0
T1	235258	102	0	0
T2	11889	6	0	0
T3	422300	156	0	0
T4	17151	21	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	102	0	0
T9	107303	58	0	0
T10	24410	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54709315	22187	0	0
T1	235258	102	0	0
T2	11889	6	0	0
T3	422300	156	0	0
T4	17151	21	0	0
T5	19513	2	0	0
T6	29595	1	0	0
T7	24210	8	0	0
T8	188643	102	0	0
T9	107303	58	0	0
T10	24410	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	228	0	0
T3	12864	2	0	0
T4	512	0	0	0
T5	584	0	0	0
T6	886	0	0	0
T7	728	0	0	0
T8	5672	0	0	0
T9	3310	0	0	0
T10	733	0	0	0
T11	369	0	0	0
T12	5678	0	0	0
T25	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T61	0	5	0	0
T68	0	1	0	0
T73	0	2	0	0
T81	0	2	0	0
T83	0	2	0	0
T90	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	8683	0	0
T1	7072	27	0	0
T2	355	2	0	0
T3	12864	54	0	0
T4	512	1	0	0
T5	584	2	0	0
T6	886	1	0	0
T7	728	8	0	0
T8	5672	27	0	0
T9	3310	25	0	0
T10	733	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	22187	0	0
T1	56463	102	0	0
T2	2851	6	0	0
T3	101363	156	0	0
T4	4115	21	0	0
T5	4682	2	0	0
T6	7102	1	0	0
T7	5812	8	0	0
T8	45270	102	0	0
T9	25758	58	0	0
T10	5857	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	22187	0	0
T1	56463	102	0	0
T2	2851	6	0	0
T3	101363	156	0	0
T4	4115	21	0	0
T5	4682	2	0	0
T6	7102	1	0	0
T7	5812	8	0	0
T8	45270	102	0	0
T9	25758	58	0	0
T10	5857	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11624004	22187	0	0
T1	53343	102	0	0
T2	2705	6	0	0
T3	88157	156	0	0
T4	2778	21	0	0
T5	4568	2	0	0
T6	7083	1	0	0
T7	5457	8	0	0
T8	42198	102	0	0
T9	20334	58	0	0
T10	5503	8	0	0