Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13130101	14408	0	0
gen_assertions[0].RstEnOn_A	13130101	1103	0	0
gen_assertions[0].RstNOff_A	13130101	14408	0	0
gen_assertions[0].RstNOn_A	13130101	1103	0	0
gen_assertions[1].RstEnOff_A	52519633	13019	0	0
gen_assertions[1].RstEnOn_A	52519633	1022	0	0
gen_assertions[1].RstNOff_A	52519633	13019	0	0
gen_assertions[1].RstNOn_A	52519633	1022	0	0
gen_assertions[2].RstEnOff_A	26260532	13093	0	0
gen_assertions[2].RstEnOn_A	26260532	1036	0	0
gen_assertions[2].RstNOff_A	26260532	13093	0	0
gen_assertions[2].RstNOn_A	26260532	1036	0	0
gen_assertions[3].RstEnOff_A	26260581	13132	0	0
gen_assertions[3].RstEnOn_A	26260581	1068	0	0
gen_assertions[3].RstNOff_A	26260581	13132	0	0
gen_assertions[3].RstNOn_A	26260581	1068	0	0
gen_assertions[4].RstEnOff_A	1658844	21967	0	0
gen_assertions[4].RstEnOn_A	1658844	1072	0	0
gen_assertions[4].RstNOff_A	1658844	21967	0	0
gen_assertions[4].RstNOn_A	1658844	1072	0	0
gen_assertions[5].RstEnOff_A	13130101	14656	0	0
gen_assertions[5].RstEnOn_A	13130101	1191	0	0
gen_assertions[5].RstNOff_A	13130101	14656	0	0
gen_assertions[5].RstNOn_A	13130101	1191	0	0
gen_assertions[6].RstEnOff_A	13130101	14634	0	0
gen_assertions[6].RstEnOn_A	13130101	1166	0	0
gen_assertions[6].RstNOff_A	13130101	14634	0	0
gen_assertions[6].RstNOn_A	13130101	1166	0	0
gen_assertions[7].RstEnOff_A	13130101	14714	0	0
gen_assertions[7].RstEnOn_A	13130101	1247	0	0
gen_assertions[7].RstNOff_A	13130101	14714	0	0
gen_assertions[7].RstNOn_A	13130101	1247	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14408	0	0
T1	56463	75	0	0
T2	2851	5	0	0
T3	101363	106	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	3	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	2	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1103	0	0
T2	2851	1	0	0
T3	101363	4	0	0
T4	4115	6	0	0
T5	4682	0	0	0
T6	7102	3	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	2	0	0
T14	0	4	0	0
T24	0	3	0	0
T25	0	11	0	0
T38	0	18	0	0
T71	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14408	0	0
T1	56463	75	0	0
T2	2851	5	0	0
T3	101363	106	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	3	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	2	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1103	0	0
T2	2851	1	0	0
T3	101363	4	0	0
T4	4115	6	0	0
T5	4682	0	0	0
T6	7102	3	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	2	0	0
T14	0	4	0	0
T24	0	3	0	0
T25	0	11	0	0
T38	0	18	0	0
T71	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52519633	13019	0	0
T1	225850	70	0	0
T2	11415	2	0	0
T3	405421	98	0	0
T4	16464	20	0	0
T5	18733	0	0	0
T6	28409	2	0	0
T7	23259	0	0	0
T8	181047	69	0	0
T9	103005	31	0	0
T10	23432	0	0	0
T11	0	1	0	0
T12	0	66	0	0
T13	0	39	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52519633	1022	0	0
T3	405421	5	0	0
T4	16464	5	0	0
T5	18733	0	0	0
T6	28409	2	0	0
T7	23259	0	0	0
T8	181047	0	0	0
T9	103005	0	0	0
T10	23432	0	0	0
T11	11846	1	0	0
T12	181185	0	0	0
T14	0	1	0	0
T24	0	3	0	0
T25	0	11	0	0
T38	0	20	0	0
T61	0	16	0	0
T71	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52519633	13019	0	0
T1	225850	70	0	0
T2	11415	2	0	0
T3	405421	98	0	0
T4	16464	20	0	0
T5	18733	0	0	0
T6	28409	2	0	0
T7	23259	0	0	0
T8	181047	69	0	0
T9	103005	31	0	0
T10	23432	0	0	0
T11	0	1	0	0
T12	0	66	0	0
T13	0	39	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52519633	1022	0	0
T3	405421	5	0	0
T4	16464	5	0	0
T5	18733	0	0	0
T6	28409	2	0	0
T7	23259	0	0	0
T8	181047	0	0	0
T9	103005	0	0	0
T10	23432	0	0	0
T11	11846	1	0	0
T12	181185	0	0	0
T14	0	1	0	0
T24	0	3	0	0
T25	0	11	0	0
T38	0	20	0	0
T61	0	16	0	0
T71	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260532	13093	0	0
T1	112939	70	0	0
T2	5705	3	0	0
T3	202709	97	0	0
T4	8231	20	0	0
T5	9365	0	0	0
T6	14205	6	0	0
T7	11618	0	0	0
T8	90536	69	0	0
T9	51510	31	0	0
T10	11707	0	0	0
T11	0	3	0	0
T12	0	66	0	0
T13	0	39	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260532	1036	0	0
T2	5705	1	0	0
T3	202709	4	0	0
T4	8231	1	0	0
T5	9365	0	0	0
T6	14205	6	0	0
T7	11618	0	0	0
T8	90536	0	0	0
T9	51510	0	0	0
T10	11707	0	0	0
T11	5922	3	0	0
T24	0	6	0	0
T25	0	11	0	0
T38	0	19	0	0
T61	0	14	0	0
T71	0	4	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260532	13093	0	0
T1	112939	70	0	0
T2	5705	3	0	0
T3	202709	97	0	0
T4	8231	20	0	0
T5	9365	0	0	0
T6	14205	6	0	0
T7	11618	0	0	0
T8	90536	69	0	0
T9	51510	31	0	0
T10	11707	0	0	0
T11	0	3	0	0
T12	0	66	0	0
T13	0	39	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260532	1036	0	0
T2	5705	1	0	0
T3	202709	4	0	0
T4	8231	1	0	0
T5	9365	0	0	0
T6	14205	6	0	0
T7	11618	0	0	0
T8	90536	0	0	0
T9	51510	0	0	0
T10	11707	0	0	0
T11	5922	3	0	0
T24	0	6	0	0
T25	0	11	0	0
T38	0	19	0	0
T61	0	14	0	0
T71	0	4	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260581	13132	0	0
T1	112938	70	0	0
T2	5708	3	0	0
T3	202715	97	0	0
T4	8232	20	0	0
T5	9366	0	0	0
T6	14206	7	0	0
T7	11617	0	0	0
T8	90543	69	0	0
T9	51516	31	0	0
T10	11715	0	0	0
T11	0	5	0	0
T12	0	66	0	0
T13	0	39	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260581	1068	0	0
T2	5708	1	0	0
T3	202715	4	0	0
T4	8232	0	0	0
T5	9366	0	0	0
T6	14206	7	0	0
T7	11617	0	0	0
T8	90543	0	0	0
T9	51516	0	0	0
T10	11715	0	0	0
T11	5922	5	0	0
T24	0	7	0	0
T25	0	10	0	0
T38	0	18	0	0
T61	0	15	0	0
T71	0	6	0	0
T72	0	6	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260581	13132	0	0
T1	112938	70	0	0
T2	5708	3	0	0
T3	202715	97	0	0
T4	8232	20	0	0
T5	9366	0	0	0
T6	14206	7	0	0
T7	11617	0	0	0
T8	90543	69	0	0
T9	51516	31	0	0
T10	11715	0	0	0
T11	0	5	0	0
T12	0	66	0	0
T13	0	39	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26260581	1068	0	0
T2	5708	1	0	0
T3	202715	4	0	0
T4	8232	0	0	0
T5	9366	0	0	0
T6	14206	7	0	0
T7	11617	0	0	0
T8	90543	0	0	0
T9	51516	0	0	0
T10	11715	0	0	0
T11	5922	5	0	0
T24	0	7	0	0
T25	0	10	0	0
T38	0	18	0	0
T61	0	15	0	0
T71	0	6	0	0
T72	0	6	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	21967	0	0
T1	7072	97	0	0
T2	355	6	0	0
T3	12864	156	0	0
T4	512	20	0	0
T5	584	2	0	0
T6	886	6	0	0
T7	728	3	0	0
T8	5672	90	0	0
T9	3310	58	0	0
T10	733	3	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	1072	0	0
T3	12864	2	0	0
T4	512	0	0	0
T5	584	0	0	0
T6	886	5	0	0
T7	728	0	0	0
T8	5672	0	0	0
T9	3310	0	0	0
T10	733	0	0	0
T11	369	5	0	0
T12	5678	0	0	0
T24	0	7	0	0
T25	0	12	0	0
T38	0	21	0	0
T61	0	15	0	0
T63	0	1	0	0
T71	0	6	0	0
T72	0	10	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	21967	0	0
T1	7072	97	0	0
T2	355	6	0	0
T3	12864	156	0	0
T4	512	20	0	0
T5	584	2	0	0
T6	886	6	0	0
T7	728	3	0	0
T8	5672	90	0	0
T9	3310	58	0	0
T10	733	3	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658844	1072	0	0
T3	12864	2	0	0
T4	512	0	0	0
T5	584	0	0	0
T6	886	5	0	0
T7	728	0	0	0
T8	5672	0	0	0
T9	3310	0	0	0
T10	733	0	0	0
T11	369	5	0	0
T12	5678	0	0	0
T24	0	7	0	0
T25	0	12	0	0
T38	0	21	0	0
T61	0	15	0	0
T63	0	1	0	0
T71	0	6	0	0
T72	0	10	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14656	0	0
T1	56463	75	0	0
T2	2851	4	0	0
T3	101363	107	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	6	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	7	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1191	0	0
T3	101363	5	0	0
T4	4115	0	0	0
T5	4682	0	0	0
T6	7102	6	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	7	0	0
T12	45304	0	0	0
T24	0	8	0	0
T25	0	14	0	0
T38	0	19	0	0
T61	0	17	0	0
T71	0	8	0	0
T72	0	14	0	0
T73	0	2	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14656	0	0
T1	56463	75	0	0
T2	2851	4	0	0
T3	101363	107	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	6	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	7	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1191	0	0
T3	101363	5	0	0
T4	4115	0	0	0
T5	4682	0	0	0
T6	7102	6	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	7	0	0
T12	45304	0	0	0
T24	0	8	0	0
T25	0	14	0	0
T38	0	19	0	0
T61	0	17	0	0
T71	0	8	0	0
T72	0	14	0	0
T73	0	2	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14634	0	0
T1	56463	75	0	0
T2	2851	4	0	0
T3	101363	105	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	7	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	7	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1166	0	0
T3	101363	3	0	0
T4	4115	0	0	0
T5	4682	0	0	0
T6	7102	7	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	7	0	0
T12	45304	0	0	0
T24	0	10	0	0
T25	0	9	0	0
T38	0	20	0	0
T61	0	17	0	0
T71	0	9	0	0
T72	0	14	0	0
T73	0	3	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14634	0	0
T1	56463	75	0	0
T2	2851	4	0	0
T3	101363	105	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	7	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	7	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1166	0	0
T3	101363	3	0	0
T4	4115	0	0	0
T5	4682	0	0	0
T6	7102	7	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	7	0	0
T12	45304	0	0	0
T24	0	10	0	0
T25	0	9	0	0
T38	0	20	0	0
T61	0	17	0	0
T71	0	9	0	0
T72	0	14	0	0
T73	0	3	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14714	0	0
T1	56463	75	0	0
T2	2851	5	0	0
T3	101363	106	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	10	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	8	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1247	0	0
T2	2851	1	0	0
T3	101363	4	0	0
T4	4115	0	0	0
T5	4682	0	0	0
T6	7102	10	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	8	0	0
T24	0	9	0	0
T25	0	12	0	0
T38	0	20	0	0
T61	0	18	0	0
T63	0	1	0	0
T71	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	14714	0	0
T1	56463	75	0	0
T2	2851	5	0	0
T3	101363	106	0	0
T4	4115	20	0	0
T5	4682	0	0	0
T6	7102	10	0	0
T7	5812	0	0	0
T8	45270	75	0	0
T9	25758	33	0	0
T10	5857	0	0	0
T11	0	8	0	0
T12	0	75	0	0
T13	0	44	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13130101	1247	0	0
T2	2851	1	0	0
T3	101363	4	0	0
T4	4115	0	0	0
T5	4682	0	0	0
T6	7102	10	0	0
T7	5812	0	0	0
T8	45270	0	0	0
T9	25758	0	0	0
T10	5857	0	0	0
T11	2960	8	0	0
T24	0	9	0	0
T25	0	12	0	0
T38	0	20	0	0
T61	0	18	0	0
T63	0	1	0	0
T71	0	10	0	0