Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12436104	7392	0	0
alert_regwen_rd_A	12436104	5276	0	0
cpu_regwen_rd_A	12436104	5723	0	0
sw_rst_ctrl_n_0_rd_A	12436104	9438	0	0
sw_rst_ctrl_n_1_rd_A	12436104	9480	0	0
sw_rst_ctrl_n_2_rd_A	12436104	9358	0	0
sw_rst_ctrl_n_3_rd_A	12436104	9362	0	0
sw_rst_ctrl_n_4_rd_A	12436104	9386	0	0
sw_rst_ctrl_n_5_rd_A	12436104	9375	0	0
sw_rst_ctrl_n_6_rd_A	12436104	9331	0	0
sw_rst_ctrl_n_7_rd_A	12436104	9396	0	0
sw_rst_regwen_0_rd_A	12436104	5883	0	0
sw_rst_regwen_1_rd_A	12436104	5797	0	0
sw_rst_regwen_2_rd_A	12436104	5728	0	0
sw_rst_regwen_3_rd_A	12436104	5725	0	0
sw_rst_regwen_4_rd_A	12436104	5744	0	0
sw_rst_regwen_5_rd_A	12436104	5952	0	0
sw_rst_regwen_6_rd_A	12436104	5974	0	0
sw_rst_regwen_7_rd_A	12436104	5877	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	7392	0	0
T47	3003	12	0	0
T48	3457	210	0	0
T49	4262	19	0	0
T50	3969	123	0	0
T51	17304	3	0	0
T74	2764	250	0	0
T75	3265	320	0	0
T76	12626	497	0	0
T77	2721	4	0	0
T80	21526	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5276	0	0
T13	39289	45	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	131	0	0
T38	51395	0	0	0
T39	40371	74	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	62	0	0
T86	0	297	0	0
T88	0	53	0	0
T107	0	34	0	0
T108	0	276	0	0
T109	0	312	0	0
T110	0	52	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5723	0	0
T13	39289	33	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	104	0	0
T38	51395	0	0	0
T39	40371	54	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	57	0	0
T86	0	301	0	0
T88	0	76	0	0
T107	0	41	0	0
T108	0	306	0	0
T109	0	373	0	0
T110	0	78	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9438	0	0
T13	39289	48	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	176	0	0
T38	51395	0	0	0
T39	40371	51	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	16	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	69	0	0
T86	0	374	0	0
T88	0	161	0	0
T107	0	16	0	0
T111	0	194	0	0
T112	0	173	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9480	0	0
T13	39289	54	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	227	0	0
T38	51395	0	0	0
T39	40371	80	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	13	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	38	0	0
T86	0	414	0	0
T88	0	180	0	0
T107	0	32	0	0
T111	0	199	0	0
T112	0	180	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9358	0	0
T13	39289	38	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	206	0	0
T38	51395	0	0	0
T39	40371	69	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	21	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	61	0	0
T86	0	393	0	0
T88	0	200	0	0
T107	0	37	0	0
T111	0	191	0	0
T112	0	215	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9362	0	0
T13	39289	25	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	158	0	0
T38	51395	0	0	0
T39	40371	93	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	18	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	67	0	0
T86	0	451	0	0
T88	0	203	0	0
T107	0	32	0	0
T111	0	208	0	0
T112	0	169	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9386	0	0
T13	39289	18	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	167	0	0
T38	51395	0	0	0
T39	40371	63	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	16	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	64	0	0
T86	0	450	0	0
T88	0	184	0	0
T107	0	23	0	0
T111	0	163	0	0
T112	0	168	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9375	0	0
T13	39289	31	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	176	0	0
T38	51395	0	0	0
T39	40371	54	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	4	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	70	0	0
T86	0	451	0	0
T88	0	245	0	0
T107	0	37	0	0
T111	0	238	0	0
T112	0	166	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9331	0	0
T13	39289	24	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	196	0	0
T38	51395	0	0	0
T39	40371	68	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	5	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	56	0	0
T86	0	430	0	0
T88	0	158	0	0
T107	0	34	0	0
T111	0	189	0	0
T112	0	164	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	9396	0	0
T13	39289	35	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	232	0	0
T38	51395	0	0	0
T39	40371	94	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	16	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	75	0	0
T86	0	421	0	0
T88	0	226	0	0
T107	0	55	0	0
T111	0	222	0	0
T112	0	163	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5883	0	0
T13	39289	49	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	70	0	0
T38	51395	0	0	0
T39	40371	86	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	12	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	68	0	0
T86	0	310	0	0
T88	0	81	0	0
T107	0	37	0	0
T111	0	29	0	0
T112	0	28	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5797	0	0
T13	39289	45	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	88	0	0
T38	51395	0	0	0
T39	40371	68	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	8	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	56	0	0
T86	0	262	0	0
T88	0	89	0	0
T107	0	31	0	0
T111	0	27	0	0
T112	0	33	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5728	0	0
T13	39289	34	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	116	0	0
T38	51395	0	0	0
T39	40371	68	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	3	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	64	0	0
T86	0	248	0	0
T88	0	86	0	0
T107	0	44	0	0
T111	0	31	0	0
T112	0	40	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5725	0	0
T13	39289	24	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	104	0	0
T38	51395	0	0	0
T39	40371	66	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	2	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	60	0	0
T86	0	287	0	0
T88	0	75	0	0
T107	0	43	0	0
T111	0	28	0	0
T112	0	30	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5744	0	0
T13	39289	39	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	124	0	0
T38	51395	0	0	0
T39	40371	74	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	6	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	53	0	0
T86	0	231	0	0
T88	0	75	0	0
T107	0	36	0	0
T111	0	47	0	0
T112	0	39	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5952	0	0
T13	39289	26	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	142	0	0
T38	51395	0	0	0
T39	40371	79	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	11	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	72	0	0
T86	0	228	0	0
T88	0	84	0	0
T107	0	37	0	0
T111	0	32	0	0
T112	0	33	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5974	0	0
T13	39289	46	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	104	0	0
T38	51395	0	0	0
T39	40371	72	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	8	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	55	0	0
T86	0	289	0	0
T88	0	80	0	0
T107	0	59	0	0
T111	0	22	0	0
T112	0	32	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12436104	5877	0	0
T13	39289	39	0	0
T14	2034	0	0	0
T24	3051	0	0	0
T25	135763	115	0	0
T38	51395	0	0	0
T39	40371	55	0	0
T55	1201	0	0	0
T67	4292	0	0	0
T69	0	13	0	0
T70	5094	0	0	0
T71	3141	0	0	0
T84	0	74	0	0
T86	0	266	0	0
T88	0	41	0	0
T107	0	28	0	0
T111	0	31	0	0
T112	0	34	0	0