Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	608643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

365884

1

T1

8

T2

734

T3

914

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	520028	1			T2	1149		T3	1356		T4	1237
values[0x0]	226898	1			T1	12		T2	483		T3	478
values[0x1]	227601	1			T1	14		T2	521		T3	524

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	511223	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

463304

1

T1

11

T2

964

T3

1146

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3764	1			T2	8		T3	10		T4	11
valid_sources[0x01]	4023	1			T2	6		T3	10		T4	6
valid_sources[0x02]	3538	1			T2	6		T3	8		T4	5
valid_sources[0x03]	2939	1			T2	5		T3	9		T4	10
valid_sources[0x04]	3318	1			T2	5		T3	13		T4	5
valid_sources[0x05]	3181	1			T2	10		T3	8		T4	8
valid_sources[0x06]	3741	1			T2	7		T3	9		T4	7
valid_sources[0x07]	3897	1			T2	8		T3	9		T4	4
valid_sources[0x08]	3557	1			T2	10		T3	12		T4	8
valid_sources[0x09]	3586	1			T2	7		T3	5		T4	5
valid_sources[0x0a]	3493	1			T2	10		T3	5		T4	6
valid_sources[0x0b]	3354	1			T2	7		T3	10		T4	9
valid_sources[0x0c]	3023	1			T2	8		T3	8		T4	11
valid_sources[0x0d]	3879	1			T2	9		T3	10		T4	8
valid_sources[0x0e]	3411	1			T2	12		T3	3		T4	8
valid_sources[0x0f]	4509	1			T2	8		T3	10		T4	9
valid_sources[0x10]	4103	1			T1	1		T2	8		T3	8
valid_sources[0x11]	4192	1			T2	5		T3	8		T4	7
valid_sources[0x12]	3956	1			T2	10		T3	10		T4	8
valid_sources[0x13]	3203	1			T2	5		T3	7		T4	4
valid_sources[0x14]	4921	1			T2	6		T3	8		T4	8
valid_sources[0x15]	3801	1			T2	8		T3	12		T4	5
valid_sources[0x16]	3012	1			T2	10		T3	7		T4	7
valid_sources[0x17]	3273	1			T2	12		T3	9		T4	8
valid_sources[0x18]	8151	1			T2	5		T3	11		T4	15
valid_sources[0x19]	4081	1			T2	13		T3	8		T4	13
valid_sources[0x1a]	3192	1			T2	7		T3	5		T4	7
valid_sources[0x1b]	4268	1			T1	1		T2	9		T3	8
valid_sources[0x1c]	3256	1			T2	4		T3	5		T4	4
valid_sources[0x1d]	3568	1			T2	5		T3	4		T4	8
valid_sources[0x1e]	3728	1			T2	6		T3	11		T4	14
valid_sources[0x1f]	3557	1			T2	7		T3	8		T4	12
valid_sources[0x20]	3435	1			T2	9		T3	11		T4	3
valid_sources[0x21]	4549	1			T2	5		T3	12		T4	8
valid_sources[0x22]	3571	1			T2	9		T3	10		T4	13
valid_sources[0x23]	3555	1			T2	10		T3	8		T4	15
valid_sources[0x24]	3524	1			T2	9		T3	10		T4	10
valid_sources[0x25]	4134	1			T1	3		T2	7		T3	14
valid_sources[0x26]	3141	1			T2	6		T3	10		T4	9
valid_sources[0x27]	3524	1			T2	18		T3	8		T4	8
valid_sources[0x28]	3282	1			T2	7		T3	9		T4	7
valid_sources[0x29]	3456	1			T2	3		T3	9		T4	14
valid_sources[0x2a]	3380	1			T2	11		T3	14		T4	3
valid_sources[0x2b]	3392	1			T2	4		T3	8		T4	7
valid_sources[0x2c]	4300	1			T2	6		T3	11		T4	6
valid_sources[0x2d]	3562	1			T2	6		T3	7		T4	4
valid_sources[0x2e]	4322	1			T2	17		T3	9		T4	4
valid_sources[0x2f]	3512	1			T2	4		T3	4		T4	10
valid_sources[0x30]	4074	1			T2	9		T3	6		T4	11
valid_sources[0x31]	3482	1			T2	11		T3	6		T4	7
valid_sources[0x32]	5286	1			T2	10		T3	10		T4	5
valid_sources[0x33]	3689	1			T2	5		T3	6		T4	6
valid_sources[0x34]	3042	1			T2	9		T3	3		T4	6
valid_sources[0x35]	4826	1			T2	7		T3	10		T4	5
valid_sources[0x36]	3848	1			T2	3		T3	6		T4	5
valid_sources[0x37]	4128	1			T2	8		T3	16		T4	9
valid_sources[0x38]	3855	1			T2	7		T3	10		T4	8
valid_sources[0x39]	3925	1			T2	12		T3	14		T4	10
valid_sources[0x3a]	3304	1			T2	5		T3	8		T4	8
valid_sources[0x3b]	3280	1			T2	9		T3	6		T4	10
valid_sources[0x3c]	4444	1			T2	8		T3	10		T4	12
valid_sources[0x3d]	3356	1			T2	9		T3	7		T4	8
valid_sources[0x3e]	3539	1			T2	6		T3	6		T4	10
valid_sources[0x3f]	4562	1			T2	10		T3	6		T4	9
valid_sources[0x40]	3937	1			T2	14		T3	15		T4	19
valid_sources[0x41]	2923	1			T2	12		T3	13		T4	9
valid_sources[0x42]	8073	1			T2	9		T3	12		T4	8
valid_sources[0x43]	6640	1			T2	5		T3	14		T4	12
valid_sources[0x44]	6456	1			T2	9		T3	7		T4	14
valid_sources[0x45]	3165	1			T2	3		T3	6		T4	6
valid_sources[0x46]	3355	1			T2	12		T3	3		T4	5
valid_sources[0x47]	3394	1			T2	2		T3	6		T4	15
valid_sources[0x48]	3629	1			T2	10		T3	17		T4	12
valid_sources[0x49]	3957	1			T2	10		T3	9		T4	13
valid_sources[0x4a]	3651	1			T2	5		T3	9		T4	9
valid_sources[0x4b]	6360	1			T2	3		T3	6		T4	8
valid_sources[0x4c]	3067	1			T2	7		T3	11		T4	8
valid_sources[0x4d]	3079	1			T2	7		T3	6		T4	5
valid_sources[0x4e]	3065	1			T1	1		T2	9		T3	5
valid_sources[0x4f]	3721	1			T2	8		T3	10		T4	7
valid_sources[0x50]	3603	1			T2	7		T3	7		T4	5
valid_sources[0x51]	3734	1			T2	5		T3	11		T4	9
valid_sources[0x52]	3221	1			T2	5		T3	6		T4	6
valid_sources[0x53]	3288	1			T2	7		T3	7		T4	5
valid_sources[0x54]	6708	1			T2	5		T3	13		T4	16
valid_sources[0x55]	6330	1			T2	7		T3	10		T4	20
valid_sources[0x56]	4048	1			T2	7		T3	11		T4	8
valid_sources[0x57]	4093	1			T2	10		T3	7		T4	10
valid_sources[0x58]	3272	1			T2	9		T3	11		T4	11
valid_sources[0x59]	3713	1			T2	12		T3	14		T4	6
valid_sources[0x5a]	3918	1			T2	6		T3	5		T4	7
valid_sources[0x5b]	3586	1			T1	3		T2	8		T3	6
valid_sources[0x5c]	3692	1			T2	13		T3	5		T4	10
valid_sources[0x5d]	3802	1			T2	13		T3	12		T4	5
valid_sources[0x5e]	3317	1			T2	14		T3	9		T4	20
valid_sources[0x5f]	3697	1			T2	9		T3	8		T4	8
valid_sources[0x60]	3370	1			T2	5		T3	10		T4	16
valid_sources[0x61]	7535	1			T2	6		T3	8		T4	11
valid_sources[0x62]	3290	1			T2	8		T3	13		T4	10
valid_sources[0x63]	3165	1			T2	6		T3	13		T4	15
valid_sources[0x64]	3643	1			T2	4		T3	7		T4	19
valid_sources[0x65]	3442	1			T2	13		T3	6		T4	10
valid_sources[0x66]	3697	1			T2	8		T3	10		T4	10
valid_sources[0x67]	3184	1			T1	1		T2	10		T3	9
valid_sources[0x68]	2604	1			T2	4		T3	7		T4	11
valid_sources[0x69]	3407	1			T2	3		T3	9		T4	16
valid_sources[0x6a]	3617	1			T2	18		T3	8		T4	5
valid_sources[0x6b]	7353	1			T2	4		T3	14		T4	12
valid_sources[0x6c]	3581	1			T2	11		T3	5		T4	8
valid_sources[0x6d]	3321	1			T2	10		T3	12		T4	12
valid_sources[0x6e]	6774	1			T1	1		T2	7		T3	6
valid_sources[0x6f]	4008	1			T2	7		T3	11		T4	8
valid_sources[0x70]	3183	1			T2	11		T3	10		T4	6
valid_sources[0x71]	3633	1			T2	12		T3	14		T4	12
valid_sources[0x72]	7081	1			T2	8		T3	13		T4	13
valid_sources[0x73]	4095	1			T2	16		T3	9		T4	3
valid_sources[0x74]	3211	1			T2	16		T3	6		T4	6
valid_sources[0x75]	3669	1			T2	6		T3	13		T4	3
valid_sources[0x76]	3996	1			T2	17		T3	8		T4	3
valid_sources[0x77]	3894	1			T2	7		T3	11		T4	4
valid_sources[0x78]	3734	1			T2	4		T3	8		T4	5
valid_sources[0x79]	3446	1			T2	4		T3	12		T4	19
valid_sources[0x7a]	5445	1			T2	8		T3	11		T4	18
valid_sources[0x7b]	3710	1			T2	15		T3	6		T4	9
valid_sources[0x7c]	3295	1			T1	2		T2	7		T3	12
valid_sources[0x7d]	3149	1			T2	10		T3	10		T4	5
valid_sources[0x7e]	3306	1			T2	6		T3	9		T4	3
valid_sources[0x7f]	4018	1			T2	12		T3	9		T4	9
valid_sources[0x80]	3704	1			T2	9		T3	7		T4	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

244202

1

T2

506

T3

667

T4

581

values[0x0]

all_enables

biggest_size

79351

1

T1

6

T2

146

T3

160

values[0x1]

all_enables

biggest_size

42331

1

T1

2

T2

82

T3

87