Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11371468	13004	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11371468	119982	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11371468	6741602	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11371468	190544	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11371468	13004	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11371468	119982	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11371468	6741602	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11371468	190544	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	13004	0	0
T2	11840	34	0	0
T3	15154	26	0	0
T4	31740	32	0	0
T5	97521	99	0	0
T6	26053	75	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	19	0	0
T11	35684	27	0	0
T12	0	4	0	0
T13	0	8	0	0
T14	0	31	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	119982	0	0
T2	11840	313	0	0
T3	15154	239	0	0
T4	31740	288	0	0
T5	97521	920	0	0
T6	26053	706	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	171	0	0
T11	35684	243	0	0
T12	0	38	0	0
T13	0	72	0	0
T14	0	285	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	6741602	0	0
T1	1939	1292	0	0
T2	11840	6295	0	0
T3	15154	6762	0	0
T4	31740	25287	0	0
T5	97521	70026	0	0
T6	26053	8770	0	0
T7	3222	2082	0	0
T8	9366	8746	0	0
T9	172976	19972	0	0
T10	5477	4581	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	190544	0	0
T2	11840	514	0	0
T3	15154	385	0	0
T4	31740	478	0	0
T5	97521	1499	0	0
T6	26053	1085	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	259	0	0
T11	35684	396	0	0
T12	0	50	0	0
T13	0	119	0	0
T14	0	471	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	13004	0	0
T2	11840	34	0	0
T3	15154	26	0	0
T4	31740	32	0	0
T5	97521	99	0	0
T6	26053	75	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	19	0	0
T11	35684	27	0	0
T12	0	4	0	0
T13	0	8	0	0
T14	0	31	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	119982	0	0
T2	11840	313	0	0
T3	15154	239	0	0
T4	31740	288	0	0
T5	97521	920	0	0
T6	26053	706	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	171	0	0
T11	35684	243	0	0
T12	0	38	0	0
T13	0	72	0	0
T14	0	285	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	6741602	0	0
T1	1939	1292	0	0
T2	11840	6295	0	0
T3	15154	6762	0	0
T4	31740	25287	0	0
T5	97521	70026	0	0
T6	26053	8770	0	0
T7	3222	2082	0	0
T8	9366	8746	0	0
T9	172976	19972	0	0
T10	5477	4581	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	190544	0	0
T2	11840	514	0	0
T3	15154	385	0	0
T4	31740	478	0	0
T5	97521	1499	0	0
T6	26053	1085	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	259	0	0
T11	35684	396	0	0
T12	0	50	0	0
T13	0	119	0	0
T14	0	471	0	0