Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T3,T4

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53529569	8609	0	0
CascadeEffAonToRstPorAboveRise_A	53529569	8609	0	0
CascadeEffAonToRstPorIoAboveFall_A	51386808	8609	0	0
CascadeEffAonToRstPorIoAboveRise_A	51386808	8609	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25694238	8609	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25694238	8609	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12846694	8609	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12846694	8609	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25694110	8609	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25694110	8609	0	0
CascadeLcToLcAboveFall_A	53529569	21613	0	0
CascadeLcToLcAboveRise_A	53529569	21613	0	0
CascadeLcToLcAonAboveFall_A	1622440	21613	0	0
CascadeLcToLcAonAboveRise_A	1622440	21613	0	0
CascadeLcToLcShadowedAboveFall_A	53529569	21613	0	0
CascadeLcToLcShadowedAboveRise_A	53529569	21613	0	0
CascadePorToAonAboveFall_A	1622440	6865	0	0
CascadeSysToSysAboveFall_A	53529569	21613	0	0
CascadeSysToSysAboveRise_A	53529569	21613	0	0
ScanRstToAonRise_A	1622440	219	0	0
StablePorToAonRise_A	1622440	8609	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11371468	21613	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11371468	21613	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11371468	21613	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11371468	21613	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12846694	21613	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12846694	21613	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11371468	21613	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11371468	21613	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11371468	21613	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11371468	21613	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	8609	0	0
T1	8159	1	0	0
T2	66402	11	0	0
T3	81462	19	0	0
T4	145647	14	0	0
T5	462760	58	0	0
T6	121897	27	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	8609	0	0
T1	8159	1	0	0
T2	66402	11	0	0
T3	81462	19	0	0
T4	145647	14	0	0
T5	462760	58	0	0
T6	121897	27	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51386808	8609	0	0
T1	7832	1	0	0
T2	63737	11	0	0
T3	78212	19	0	0
T4	139804	14	0	0
T5	444245	58	0	0
T6	117018	27	0	0
T7	13627	2	0	0
T8	37635	1	0	0
T9	791855	271	0	0
T10	26038	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51386808	8609	0	0
T1	7832	1	0	0
T2	63737	11	0	0
T3	78212	19	0	0
T4	139804	14	0	0
T5	444245	58	0	0
T6	117018	27	0	0
T7	13627	2	0	0
T8	37635	1	0	0
T9	791855	271	0	0
T10	26038	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694238	8609	0	0
T1	3915	1	0	0
T2	31863	11	0	0
T3	39106	19	0	0
T4	69897	14	0	0
T5	222118	58	0	0
T6	58525	27	0	0
T7	6810	2	0	0
T8	18819	1	0	0
T9	396000	271	0	0
T10	13018	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694238	8609	0	0
T1	3915	1	0	0
T2	31863	11	0	0
T3	39106	19	0	0
T4	69897	14	0	0
T5	222118	58	0	0
T6	58525	27	0	0
T7	6810	2	0	0
T8	18819	1	0	0
T9	396000	271	0	0
T10	13018	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	8609	0	0
T1	1956	1	0	0
T2	15933	11	0	0
T3	19551	19	0	0
T4	34945	14	0	0
T5	111064	58	0	0
T6	29260	27	0	0
T7	3405	2	0	0
T8	9408	1	0	0
T9	198022	271	0	0
T10	6508	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	8609	0	0
T1	1956	1	0	0
T2	15933	11	0	0
T3	19551	19	0	0
T4	34945	14	0	0
T5	111064	58	0	0
T6	29260	27	0	0
T7	3405	2	0	0
T8	9408	1	0	0
T9	198022	271	0	0
T10	6508	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694110	8609	0	0
T1	3915	1	0	0
T2	31874	11	0	0
T3	39111	19	0	0
T4	69905	14	0	0
T5	222129	58	0	0
T6	58519	27	0	0
T7	6811	2	0	0
T8	18819	1	0	0
T9	395978	271	0	0
T10	13018	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694110	8609	0	0
T1	3915	1	0	0
T2	31874	11	0	0
T3	39111	19	0	0
T4	69905	14	0	0
T5	222129	58	0	0
T6	58519	27	0	0
T7	6811	2	0	0
T8	18819	1	0	0
T9	395978	271	0	0
T10	13018	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	21613	0	0
T1	8159	1	0	0
T2	66402	45	0	0
T3	81462	45	0	0
T4	145647	46	0	0
T5	462760	157	0	0
T6	121897	102	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	20	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	21613	0	0
T1	8159	1	0	0
T2	66402	45	0	0
T3	81462	45	0	0
T4	145647	46	0	0
T5	462760	157	0	0
T6	121897	102	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	20	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	21613	0	0
T1	243	1	0	0
T2	2051	45	0	0
T3	2483	45	0	0
T4	4474	46	0	0
T5	14158	157	0	0
T6	3671	102	0	0
T7	425	2	0	0
T8	1175	1	0	0
T9	24872	271	0	0
T10	813	20	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	21613	0	0
T1	243	1	0	0
T2	2051	45	0	0
T3	2483	45	0	0
T4	4474	46	0	0
T5	14158	157	0	0
T6	3671	102	0	0
T7	425	2	0	0
T8	1175	1	0	0
T9	24872	271	0	0
T10	813	20	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	21613	0	0
T1	8159	1	0	0
T2	66402	45	0	0
T3	81462	45	0	0
T4	145647	46	0	0
T5	462760	157	0	0
T6	121897	102	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	20	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	21613	0	0
T1	8159	1	0	0
T2	66402	45	0	0
T3	81462	45	0	0
T4	145647	46	0	0
T5	462760	157	0	0
T6	121897	102	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	20	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	6865	0	0
T1	243	1	0	0
T2	2051	7	0	0
T3	2483	8	0	0
T4	4474	7	0	0
T5	14158	33	0	0
T6	3671	27	0	0
T7	425	2	0	0
T8	1175	1	0	0
T9	24872	271	0	0
T10	813	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	21613	0	0
T1	8159	1	0	0
T2	66402	45	0	0
T3	81462	45	0	0
T4	145647	46	0	0
T5	462760	157	0	0
T6	121897	102	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	20	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53529569	21613	0	0
T1	8159	1	0	0
T2	66402	45	0	0
T3	81462	45	0	0
T4	145647	46	0	0
T5	462760	157	0	0
T6	121897	102	0	0
T7	14188	2	0	0
T8	39204	1	0	0
T9	825048	271	0	0
T10	27124	20	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	219	0	0
T4	4474	1	0	0
T5	14158	0	0	0
T6	3671	0	0	0
T7	425	0	0	0
T8	1175	0	0	0
T9	24872	0	0	0
T10	813	0	0	0
T11	5123	1	0	0
T12	739	0	0	0
T13	379	0	0	0
T14	0	1	0	0
T27	0	2	0	0
T50	0	4	0	0
T91	0	1	0	0
T97	0	1	0	0
T98	0	7	0	0
T128	0	1	0	0
T129	0	2	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	8609	0	0
T1	243	1	0	0
T2	2051	11	0	0
T3	2483	19	0	0
T4	4474	14	0	0
T5	14158	58	0	0
T6	3671	27	0	0
T7	425	2	0	0
T8	1175	1	0	0
T9	24872	271	0	0
T10	813	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	21613	0	0
T1	1956	1	0	0
T2	15933	45	0	0
T3	19551	45	0	0
T4	34945	46	0	0
T5	111064	157	0	0
T6	29260	102	0	0
T7	3405	2	0	0
T8	9408	1	0	0
T9	198022	271	0	0
T10	6508	20	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	21613	0	0
T1	1956	1	0	0
T2	15933	45	0	0
T3	19551	45	0	0
T4	34945	46	0	0
T5	111064	157	0	0
T6	29260	102	0	0
T7	3405	2	0	0
T8	9408	1	0	0
T9	198022	271	0	0
T10	6508	20	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11371468	21613	0	0
T1	1939	1	0	0
T2	11840	45	0	0
T3	15154	45	0	0
T4	31740	46	0	0
T5	97521	157	0	0
T6	26053	102	0	0
T7	3222	2	0	0
T8	9366	1	0	0
T9	172976	271	0	0
T10	5477	20	0	0