Unified Coverage Report :: Module :: prim_generic_clock

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

Module Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_aon_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_pd_n[0].u_rst_pd_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							g_scan_mux.u_scan_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_root_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_clean_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_out_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1274271	1241951	0	0
selKnown1	177920	145600	0	0

selKnown0

Name	Attempts	Real Successes
Total	1274271	1241951
T2	2570	2506
T3	2635	2571
T4	2649	2585
T5	9239	9175
T6	5853	5789
T7	166	102
T8	157	93
T9	17344	17280
T10	1109	1045
T11	2947	2883
T12	0	243
T14	0	162
T50	0	55

selKnown1

Name	Attempts	Real Successes
Total	177920	145600
T2	320	256
T3	768	704
T4	512	448
T5	1664	1600
T6	64	0
T7	64	0
T8	64	0
T9	64	0
T10	64	0
T11	704	640
T12	0	64
T14	0	576
T49	0	64
T50	0	2752
T73	0	64

Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8609	8104	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	8609	8104
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8609	8104	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	8609	8104
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8609	8104	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	8609	8104
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8609	8104	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	8609	8104
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8609	8104	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	8609	8104
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21548	21043	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21548	21043
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21613	21108	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21613	21108
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22471	21966	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22471	21966
T2	45	44
T3	45	44
T4	46	45
T5	169	168
T6	102	101
T7	7	6
T8	10	9
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22529	22024	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22529	22024
T2	45	44
T3	45	44
T4	46	45
T5	166	165
T6	102	101
T7	8	7
T8	11	10
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22582	22077	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22582	22077
T2	45	44
T3	45	44
T4	46	45
T5	173	172
T6	102	101
T7	6	5
T8	9	8
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22636	22131	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22636	22131
T2	45	44
T3	45	44
T4	46	45
T5	171	170
T6	102	101
T7	7	6
T8	12	11
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22675	22170	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22675	22170
T2	45	44
T3	45	44
T4	46	45
T5	173	172
T6	102	101
T7	6	5
T8	12	11
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21548	21043	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21548	21043
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22703	22198	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22703	22198
T2	45	44
T3	45	44
T4	46	45
T5	170	169
T6	102	101
T7	8	7
T8	14	13
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22768	22263	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22768	22263
T2	45	44
T3	45	44
T4	46	45
T5	171	170
T6	102	101
T7	6	5
T8	17	16
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	22841	22336	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	22841	22336
T2	45	44
T3	45	44
T4	46	45
T5	170	169
T6	102	101
T7	6	5
T8	16	15
T9	271	270
T10	20	19
T11	50	49

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	21663	21158	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	21663	21158
T2	45	44
T3	45	44
T4	46	45
T5	157	156
T6	102	101
T7	2	1
T8	1	0
T9	271	270
T10	20	19
T11	50	49
T12	0	5

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	6850	6345	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	6850	6345
T2	7	6
T3	8	7
T4	7	6
T5	33	32
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	13	12
T14	0	10
T50	0	55

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	9072	8567	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	9072	8567
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8609	8104	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	8609	8104
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

Line No.	Covered	Statements
17	1	1

Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	8609	8104	0	0
selKnown1	2780	2275	0	0

selKnown0

Name	Attempts	Real Successes
Total	8609	8104
T2	11	10
T3	19	18
T4	14	13
T5	58	57
T6	27	26
T7	2	1
T8	1	0
T9	271	270
T10	1	0
T11	23	22
T12	0	1
T14	0	19

selKnown1

Name	Attempts	Real Successes
Total	2780	2275
T2	5	4
T3	12	11
T4	8	7
T5	26	25
T6	1	0
T7	1	0
T8	1	0
T9	1	0
T10	1	0
T11	11	10
T12	0	1
T14	0	9
T49	0	1
T50	0	43
T73	0	1