Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T8
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12846694	13862	0	0
gen_assertions[0].RstEnOn_A	12846694	1050	0	0
gen_assertions[0].RstNOff_A	12846694	13862	0	0
gen_assertions[0].RstNOn_A	12846694	1050	0	0
gen_assertions[1].RstEnOff_A	51386808	12560	0	0
gen_assertions[1].RstEnOn_A	51386808	1048	0	0
gen_assertions[1].RstNOff_A	51386808	12560	0	0
gen_assertions[1].RstNOn_A	51386808	1048	0	0
gen_assertions[2].RstEnOff_A	25694238	12613	0	0
gen_assertions[2].RstEnOn_A	25694238	1025	0	0
gen_assertions[2].RstNOff_A	25694238	12613	0	0
gen_assertions[2].RstNOn_A	25694238	1025	0	0
gen_assertions[3].RstEnOff_A	25694110	12667	0	0
gen_assertions[3].RstEnOn_A	25694110	1061	0	0
gen_assertions[3].RstNOff_A	25694110	12667	0	0
gen_assertions[3].RstNOn_A	25694110	1061	0	0
gen_assertions[4].RstEnOff_A	1622440	21340	0	0
gen_assertions[4].RstEnOn_A	1622440	1113	0	0
gen_assertions[4].RstNOff_A	1622440	21340	0	0
gen_assertions[4].RstNOn_A	1622440	1113	0	0
gen_assertions[5].RstEnOff_A	12846694	14094	0	0
gen_assertions[5].RstEnOn_A	12846694	1131	0	0
gen_assertions[5].RstNOff_A	12846694	14094	0	0
gen_assertions[5].RstNOn_A	12846694	1131	0	0
gen_assertions[6].RstEnOff_A	12846694	14159	0	0
gen_assertions[6].RstEnOn_A	12846694	1196	0	0
gen_assertions[6].RstNOff_A	12846694	14159	0	0
gen_assertions[6].RstNOn_A	12846694	1196	0	0
gen_assertions[7].RstEnOff_A	12846694	14232	0	0
gen_assertions[7].RstEnOn_A	12846694	1257	0	0
gen_assertions[7].RstNOff_A	12846694	14232	0	0
gen_assertions[7].RstNOn_A	12846694	1257	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	13862	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	111	0	0
T6	29260	75	0	0
T7	3405	5	0	0
T8	9408	9	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1050	0	0
T5	111064	13	0	0
T6	29260	0	0	0
T7	3405	6	0	0
T8	9408	9	0	0
T9	198022	0	0	0
T10	6508	2	0	0
T11	40295	0	0	0
T12	5915	1	0	0
T13	3048	2	0	0
T14	20966	0	0	0
T27	0	26	0	0
T50	0	14	0	0
T67	0	5	0	0
T73	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	13862	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	111	0	0
T6	29260	75	0	0
T7	3405	5	0	0
T8	9408	9	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1050	0	0
T5	111064	13	0	0
T6	29260	0	0	0
T7	3405	6	0	0
T8	9408	9	0	0
T9	198022	0	0	0
T10	6508	2	0	0
T11	40295	0	0	0
T12	5915	1	0	0
T13	3048	2	0	0
T14	20966	0	0	0
T27	0	26	0	0
T50	0	14	0	0
T67	0	5	0	0
T73	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51386808	12560	0	0
T2	63737	33	0	0
T3	78212	23	0	0
T4	139804	27	0	0
T5	444245	104	0	0
T6	117018	68	0	0
T7	13627	6	0	0
T8	37635	10	0	0
T9	791855	0	0	0
T10	26038	15	0	0
T11	161153	22	0	0
T12	0	2	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51386808	1048	0	0
T5	444245	10	0	0
T6	117018	0	0	0
T7	13627	7	0	0
T8	37635	10	0	0
T9	791855	0	0	0
T10	26038	0	0	0
T11	161153	0	0	0
T12	23660	0	0	0
T13	12197	0	0	0
T14	83864	0	0	0
T27	0	26	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	5	0	0
T50	0	17	0	0
T57	0	7	0	0
T67	0	5	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51386808	12560	0	0
T2	63737	33	0	0
T3	78212	23	0	0
T4	139804	27	0	0
T5	444245	104	0	0
T6	117018	68	0	0
T7	13627	6	0	0
T8	37635	10	0	0
T9	791855	0	0	0
T10	26038	15	0	0
T11	161153	22	0	0
T12	0	2	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51386808	1048	0	0
T5	444245	10	0	0
T6	117018	0	0	0
T7	13627	7	0	0
T8	37635	10	0	0
T9	791855	0	0	0
T10	26038	0	0	0
T11	161153	0	0	0
T12	23660	0	0	0
T13	12197	0	0	0
T14	83864	0	0	0
T27	0	26	0	0
T28	0	2	0	0
T30	0	1	0	0
T31	0	5	0	0
T50	0	17	0	0
T57	0	7	0	0
T67	0	5	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694238	12613	0	0
T2	31863	33	0	0
T3	39106	23	0	0
T4	69897	27	0	0
T5	222118	111	0	0
T6	58525	68	0	0
T7	6810	4	0	0
T8	18819	8	0	0
T9	396000	0	0	0
T10	13018	15	0	0
T11	80586	22	0	0
T12	0	2	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694238	1025	0	0
T5	222118	16	0	0
T6	58525	0	0	0
T7	6810	4	0	0
T8	18819	8	0	0
T9	396000	0	0	0
T10	13018	0	0	0
T11	80586	0	0	0
T12	11831	0	0	0
T13	6098	0	0	0
T14	41941	0	0	0
T27	0	31	0	0
T28	0	3	0	0
T30	0	1	0	0
T31	0	6	0	0
T50	0	17	0	0
T67	0	4	0	0
T73	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694238	12613	0	0
T2	31863	33	0	0
T3	39106	23	0	0
T4	69897	27	0	0
T5	222118	111	0	0
T6	58525	68	0	0
T7	6810	4	0	0
T8	18819	8	0	0
T9	396000	0	0	0
T10	13018	15	0	0
T11	80586	22	0	0
T12	0	2	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694238	1025	0	0
T5	222118	16	0	0
T6	58525	0	0	0
T7	6810	4	0	0
T8	18819	8	0	0
T9	396000	0	0	0
T10	13018	0	0	0
T11	80586	0	0	0
T12	11831	0	0	0
T13	6098	0	0	0
T14	41941	0	0	0
T27	0	31	0	0
T28	0	3	0	0
T30	0	1	0	0
T31	0	6	0	0
T50	0	17	0	0
T67	0	4	0	0
T73	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694110	12667	0	0
T2	31874	33	0	0
T3	39111	23	0	0
T4	69905	27	0	0
T5	222129	109	0	0
T6	58519	68	0	0
T7	6811	5	0	0
T8	18819	11	0	0
T9	395978	0	0	0
T10	13018	15	0	0
T11	80589	22	0	0
T12	0	2	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694110	1061	0	0
T5	222129	15	0	0
T6	58519	0	0	0
T7	6811	5	0	0
T8	18819	11	0	0
T9	395978	0	0	0
T10	13018	0	0	0
T11	80589	0	0	0
T12	11830	0	0	0
T13	6099	0	0	0
T14	41938	0	0	0
T27	0	20	0	0
T28	0	5	0	0
T31	0	9	0	0
T42	0	1	0	0
T50	0	17	0	0
T57	0	8	0	0
T67	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694110	12667	0	0
T2	31874	33	0	0
T3	39111	23	0	0
T4	69905	27	0	0
T5	222129	109	0	0
T6	58519	68	0	0
T7	6811	5	0	0
T8	18819	11	0	0
T9	395978	0	0	0
T10	13018	15	0	0
T11	80589	22	0	0
T12	0	2	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25694110	1061	0	0
T5	222129	15	0	0
T6	58519	0	0	0
T7	6811	5	0	0
T8	18819	11	0	0
T9	395978	0	0	0
T10	13018	0	0	0
T11	80589	0	0	0
T12	11830	0	0	0
T13	6099	0	0	0
T14	41938	0	0	0
T27	0	20	0	0
T28	0	5	0	0
T31	0	9	0	0
T42	0	1	0	0
T50	0	17	0	0
T57	0	8	0	0
T67	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	21340	0	0
T1	243	1	0	0
T2	2051	45	0	0
T3	2483	45	0	0
T4	4474	44	0	0
T5	14158	173	0	0
T6	3671	74	0	0
T7	425	5	0	0
T8	1175	12	0	0
T9	24872	271	0	0
T10	813	19	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	1113	0	0
T5	14158	16	0	0
T6	3671	0	0	0
T7	425	4	0	0
T8	1175	11	0	0
T9	24872	0	0	0
T10	813	0	0	0
T11	5123	0	0	0
T12	739	1	0	0
T13	379	0	0	0
T14	2694	0	0	0
T27	0	26	0	0
T28	0	6	0	0
T31	0	11	0	0
T42	0	1	0	0
T50	0	19	0	0
T67	0	9	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	21340	0	0
T1	243	1	0	0
T2	2051	45	0	0
T3	2483	45	0	0
T4	4474	44	0	0
T5	14158	173	0	0
T6	3671	74	0	0
T7	425	5	0	0
T8	1175	12	0	0
T9	24872	271	0	0
T10	813	19	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1622440	1113	0	0
T5	14158	16	0	0
T6	3671	0	0	0
T7	425	4	0	0
T8	1175	11	0	0
T9	24872	0	0	0
T10	813	0	0	0
T11	5123	0	0	0
T12	739	1	0	0
T13	379	0	0	0
T14	2694	0	0	0
T27	0	26	0	0
T28	0	6	0	0
T31	0	11	0	0
T42	0	1	0	0
T50	0	19	0	0
T67	0	9	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	14094	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	112	0	0
T6	29260	75	0	0
T7	3405	6	0	0
T8	9408	13	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1131	0	0
T5	111064	15	0	0
T6	29260	0	0	0
T7	3405	7	0	0
T8	9408	13	0	0
T9	198022	0	0	0
T10	6508	0	0	0
T11	40295	0	0	0
T12	5915	0	0	0
T13	3048	0	0	0
T14	20966	0	0	0
T27	0	30	0	0
T28	0	7	0	0
T31	0	12	0	0
T50	0	13	0	0
T57	0	12	0	0
T67	0	6	0	0
T73	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	14094	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	112	0	0
T6	29260	75	0	0
T7	3405	6	0	0
T8	9408	13	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1131	0	0
T5	111064	15	0	0
T6	29260	0	0	0
T7	3405	7	0	0
T8	9408	13	0	0
T9	198022	0	0	0
T10	6508	0	0	0
T11	40295	0	0	0
T12	5915	0	0	0
T13	3048	0	0	0
T14	20966	0	0	0
T27	0	30	0	0
T28	0	7	0	0
T31	0	12	0	0
T50	0	13	0	0
T57	0	12	0	0
T67	0	6	0	0
T73	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	14159	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	113	0	0
T6	29260	75	0	0
T7	3405	4	0	0
T8	9408	16	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	5	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1196	0	0
T5	111064	15	0	0
T6	29260	0	0	0
T7	3405	5	0	0
T8	9408	16	0	0
T9	198022	0	0	0
T10	6508	0	0	0
T11	40295	0	0	0
T12	5915	1	0	0
T13	3048	0	0	0
T14	20966	0	0	0
T27	0	29	0	0
T28	0	7	0	0
T31	0	13	0	0
T50	0	11	0	0
T57	0	9	0	0
T67	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	14159	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	113	0	0
T6	29260	75	0	0
T7	3405	4	0	0
T8	9408	16	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	5	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1196	0	0
T5	111064	15	0	0
T6	29260	0	0	0
T7	3405	5	0	0
T8	9408	16	0	0
T9	198022	0	0	0
T10	6508	0	0	0
T11	40295	0	0	0
T12	5915	1	0	0
T13	3048	0	0	0
T14	20966	0	0	0
T27	0	29	0	0
T28	0	7	0	0
T31	0	13	0	0
T50	0	11	0	0
T57	0	9	0	0
T67	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	14232	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	112	0	0
T6	29260	75	0	0
T7	3405	4	0	0
T8	9408	15	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1257	0	0
T5	111064	14	0	0
T6	29260	0	0	0
T7	3405	4	0	0
T8	9408	15	0	0
T9	198022	0	0	0
T10	6508	0	0	0
T11	40295	0	0	0
T12	5915	0	0	0
T13	3048	0	0	0
T14	20966	0	0	0
T27	0	25	0	0
T28	0	9	0	0
T31	0	13	0	0
T50	0	16	0	0
T57	0	12	0	0
T59	0	1	0	0
T67	0	12	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	14232	0	0
T2	15933	34	0	0
T3	19551	26	0	0
T4	34945	32	0	0
T5	111064	112	0	0
T6	29260	75	0	0
T7	3405	4	0	0
T8	9408	15	0	0
T9	198022	0	0	0
T10	6508	19	0	0
T11	40295	27	0	0
T12	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12846694	1257	0	0
T5	111064	14	0	0
T6	29260	0	0	0
T7	3405	4	0	0
T8	9408	15	0	0
T9	198022	0	0	0
T10	6508	0	0	0
T11	40295	0	0	0
T12	5915	0	0	0
T13	3048	0	0	0
T14	20966	0	0	0
T27	0	25	0	0
T28	0	9	0	0
T31	0	13	0	0
T50	0	16	0	0
T57	0	12	0	0
T59	0	1	0	0
T67	0	12	0	0