Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12094423	9158	0	0
alert_regwen_rd_A	12094423	5207	0	0
cpu_regwen_rd_A	12094423	5076	0	0
sw_rst_ctrl_n_0_rd_A	12094423	9564	0	0
sw_rst_ctrl_n_1_rd_A	12094423	9581	0	0
sw_rst_ctrl_n_2_rd_A	12094423	9648	0	0
sw_rst_ctrl_n_3_rd_A	12094423	10022	0	0
sw_rst_ctrl_n_4_rd_A	12094423	9803	0	0
sw_rst_ctrl_n_5_rd_A	12094423	9595	0	0
sw_rst_ctrl_n_6_rd_A	12094423	9592	0	0
sw_rst_ctrl_n_7_rd_A	12094423	9886	0	0
sw_rst_regwen_0_rd_A	12094423	5773	0	0
sw_rst_regwen_1_rd_A	12094423	5747	0	0
sw_rst_regwen_2_rd_A	12094423	5905	0	0
sw_rst_regwen_3_rd_A	12094423	5671	0	0
sw_rst_regwen_4_rd_A	12094423	5610	0	0
sw_rst_regwen_5_rd_A	12094423	5777	0	0
sw_rst_regwen_6_rd_A	12094423	5614	0	0
sw_rst_regwen_7_rd_A	12094423	5466	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9158	0	0
T69	9398	2	0	0
T72	2664	41	0	0
T74	9453	470	0	0
T75	6479	276	0	0
T76	6194	385	0	0
T80	2652	53	0	0
T85	2999	133	0	0
T86	4436	18	0	0
T87	3724	101	0	0
T88	2587	3	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5207	0	0
T4	31740	59	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	39	0	0
T12	5771	0	0	0
T13	2552	0	0	0
T50	0	254	0	0
T93	0	71	0	0
T95	0	418	0	0
T97	0	38	0	0
T122	0	25	0	0
T123	0	30	0	0
T124	0	97	0	0
T125	0	85	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5076	0	0
T4	31740	40	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	21	0	0
T12	5771	0	0	0
T13	2552	0	0	0
T50	0	240	0	0
T93	0	73	0	0
T95	0	432	0	0
T97	0	34	0	0
T122	0	30	0	0
T123	0	35	0	0
T124	0	86	0	0
T125	0	64	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9564	0	0
T4	31740	38	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	67	0	0
T11	35684	36	0	0
T12	5771	19	0	0
T13	2552	0	0	0
T25	0	28	0	0
T31	0	169	0	0
T50	0	504	0	0
T57	0	169	0	0
T58	0	56	0	0
T97	0	195	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9581	0	0
T4	31740	40	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	96	0	0
T11	35684	45	0	0
T12	5771	10	0	0
T13	2552	0	0	0
T25	0	26	0	0
T31	0	214	0	0
T50	0	506	0	0
T57	0	172	0	0
T58	0	63	0	0
T97	0	158	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9648	0	0
T4	31740	49	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	65	0	0
T11	35684	49	0	0
T12	5771	10	0	0
T13	2552	0	0	0
T25	0	43	0	0
T31	0	209	0	0
T50	0	467	0	0
T57	0	170	0	0
T58	0	50	0	0
T97	0	198	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	10022	0	0
T4	31740	53	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	66	0	0
T11	35684	57	0	0
T12	5771	19	0	0
T13	2552	0	0	0
T25	0	29	0	0
T31	0	192	0	0
T50	0	470	0	0
T57	0	194	0	0
T58	0	53	0	0
T97	0	134	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9803	0	0
T4	31740	33	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	58	0	0
T11	35684	40	0	0
T12	5771	8	0	0
T13	2552	0	0	0
T25	0	34	0	0
T31	0	172	0	0
T50	0	465	0	0
T57	0	204	0	0
T58	0	34	0	0
T97	0	150	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9595	0	0
T4	31740	56	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	68	0	0
T11	35684	59	0	0
T12	5771	7	0	0
T13	2552	0	0	0
T25	0	38	0	0
T31	0	169	0	0
T50	0	452	0	0
T57	0	177	0	0
T58	0	50	0	0
T97	0	151	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9592	0	0
T4	31740	50	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	82	0	0
T11	35684	39	0	0
T12	5771	8	0	0
T13	2552	0	0	0
T25	0	27	0	0
T31	0	194	0	0
T50	0	413	0	0
T57	0	188	0	0
T58	0	64	0	0
T97	0	186	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	9886	0	0
T4	31740	53	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	54	0	0
T11	35684	24	0	0
T12	5771	15	0	0
T13	2552	0	0	0
T25	0	29	0	0
T31	0	229	0	0
T50	0	475	0	0
T57	0	201	0	0
T58	0	72	0	0
T97	0	161	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5773	0	0
T4	31740	27	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	45	0	0
T12	5771	1	0	0
T13	2552	0	0	0
T31	0	22	0	0
T50	0	281	0	0
T57	0	30	0	0
T93	0	77	0	0
T97	0	70	0	0
T126	0	32	0	0
T127	0	36	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5747	0	0
T4	31740	46	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	51	0	0
T12	5771	10	0	0
T13	2552	0	0	0
T31	0	32	0	0
T50	0	229	0	0
T57	0	25	0	0
T93	0	61	0	0
T97	0	38	0	0
T126	0	44	0	0
T127	0	40	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5905	0	0
T4	31740	38	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	47	0	0
T12	5771	6	0	0
T13	2552	0	0	0
T31	0	23	0	0
T50	0	259	0	0
T57	0	33	0	0
T93	0	61	0	0
T97	0	25	0	0
T126	0	41	0	0
T127	0	40	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5671	0	0
T4	31740	38	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	29	0	0
T12	5771	6	0	0
T13	2552	0	0	0
T31	0	34	0	0
T50	0	288	0	0
T57	0	35	0	0
T93	0	76	0	0
T97	0	30	0	0
T126	0	28	0	0
T127	0	48	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5610	0	0
T4	31740	27	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	31	0	0
T12	5771	13	0	0
T13	2552	0	0	0
T31	0	25	0	0
T50	0	294	0	0
T57	0	30	0	0
T93	0	63	0	0
T97	0	43	0	0
T126	0	63	0	0
T127	0	37	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5777	0	0
T4	31740	33	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	32	0	0
T12	5771	14	0	0
T13	2552	0	0	0
T31	0	25	0	0
T50	0	251	0	0
T57	0	29	0	0
T93	0	70	0	0
T97	0	22	0	0
T126	0	34	0	0
T127	0	32	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5614	0	0
T4	31740	51	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	46	0	0
T12	5771	10	0	0
T13	2552	0	0	0
T31	0	33	0	0
T50	0	264	0	0
T57	0	24	0	0
T93	0	48	0	0
T97	0	38	0	0
T126	0	24	0	0
T127	0	49	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12094423	5466	0	0
T4	31740	50	0	0
T5	97521	0	0	0
T6	26053	0	0	0
T7	3222	0	0	0
T8	9366	0	0	0
T9	172976	0	0	0
T10	5477	0	0	0
T11	35684	36	0	0
T12	5771	1	0	0
T13	2552	0	0	0
T31	0	26	0	0
T50	0	272	0	0
T57	0	29	0	0
T93	0	58	0	0
T97	0	44	0	0
T126	0	34	0	0
T127	0	45	0	0