Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	632342	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

379639

1

T2

1932

T3

2288

T4

1005

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	540507	1			T2	2844		T3	3516		T4	1601
values[0x0]	235556	1			T2	1172		T3	1347		T4	619
values[0x1]	235918	1			T2	1206		T3	1309		T4	582

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	531053	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

480928

1

T2

2473

T3

2921

T4

1266

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3909	1			T2	12		T4	12		T5	2
valid_sources[0x01]	7206	1			T2	14		T4	15		T8	27
valid_sources[0x02]	3546	1			T2	10		T3	369		T4	10
valid_sources[0x03]	3838	1			T2	9		T4	6		T5	1
valid_sources[0x04]	3752	1			T2	10		T3	13		T4	6
valid_sources[0x05]	3157	1			T2	27		T4	14		T5	1
valid_sources[0x06]	3609	1			T2	27		T4	8		T8	50
valid_sources[0x07]	3575	1			T2	23		T4	12		T5	2
valid_sources[0x08]	3674	1			T2	9		T4	8		T5	1
valid_sources[0x09]	3590	1			T2	27		T4	10		T5	2
valid_sources[0x0a]	5002	1			T2	17		T4	14		T5	3
valid_sources[0x0b]	3377	1			T2	29		T4	10		T5	5
valid_sources[0x0c]	3455	1			T2	22		T4	10		T5	3
valid_sources[0x0d]	3117	1			T2	14		T3	4		T4	9
valid_sources[0x0e]	3604	1			T2	15		T4	6		T8	26
valid_sources[0x0f]	4282	1			T2	22		T4	13		T5	2
valid_sources[0x10]	3309	1			T2	12		T4	10		T5	2
valid_sources[0x11]	3578	1			T2	22		T4	13		T5	3
valid_sources[0x12]	4482	1			T2	30		T4	7		T5	1
valid_sources[0x13]	3393	1			T2	11		T4	9		T5	2
valid_sources[0x14]	3702	1			T2	23		T4	7		T5	3
valid_sources[0x15]	4017	1			T2	41		T4	13		T5	3
valid_sources[0x16]	3800	1			T2	14		T3	58		T4	13
valid_sources[0x17]	3428	1			T2	16		T4	14		T5	1
valid_sources[0x18]	3426	1			T2	24		T4	11		T5	1
valid_sources[0x19]	4943	1			T2	23		T3	154		T4	10
valid_sources[0x1a]	3891	1			T2	31		T3	5		T4	9
valid_sources[0x1b]	3872	1			T2	28		T3	2		T4	4
valid_sources[0x1c]	3948	1			T2	18		T4	10		T5	1
valid_sources[0x1d]	3787	1			T2	41		T3	140		T4	9
valid_sources[0x1e]	3617	1			T2	13		T4	6		T8	44
valid_sources[0x1f]	3386	1			T2	24		T3	112		T4	16
valid_sources[0x20]	3876	1			T2	22		T4	11		T5	1
valid_sources[0x21]	3508	1			T2	15		T3	10		T4	17
valid_sources[0x22]	6990	1			T2	22		T4	13		T5	1
valid_sources[0x23]	4007	1			T2	9		T4	10		T5	1
valid_sources[0x24]	3251	1			T2	24		T4	12		T8	33
valid_sources[0x25]	3328	1			T2	20		T4	15		T5	1
valid_sources[0x26]	3681	1			T2	20		T4	4		T5	3
valid_sources[0x27]	4241	1			T2	23		T4	10		T5	1
valid_sources[0x28]	3371	1			T2	34		T4	13		T8	37
valid_sources[0x29]	3479	1			T2	24		T3	1		T4	12
valid_sources[0x2a]	3760	1			T2	21		T4	12		T5	4
valid_sources[0x2b]	4266	1			T2	19		T3	108		T4	12
valid_sources[0x2c]	3204	1			T2	34		T4	7		T5	3
valid_sources[0x2d]	3434	1			T2	25		T4	10		T5	1
valid_sources[0x2e]	3864	1			T2	9		T4	13		T5	1
valid_sources[0x2f]	3711	1			T2	19		T3	70		T4	15
valid_sources[0x30]	4470	1			T2	15		T4	13		T8	45
valid_sources[0x31]	3601	1			T2	25		T4	9		T5	1
valid_sources[0x32]	3890	1			T2	37		T3	16		T4	12
valid_sources[0x33]	3835	1			T2	19		T4	11		T5	1
valid_sources[0x34]	4474	1			T2	38		T4	6		T5	3
valid_sources[0x35]	3681	1			T2	4		T3	13		T4	7
valid_sources[0x36]	3420	1			T2	8		T4	7		T5	1
valid_sources[0x37]	3921	1			T2	8		T3	7		T4	10
valid_sources[0x38]	3585	1			T2	25		T4	7		T5	2
valid_sources[0x39]	3446	1			T2	18		T4	9		T5	2
valid_sources[0x3a]	4572	1			T2	36		T4	14		T5	1
valid_sources[0x3b]	3941	1			T2	27		T4	12		T5	2
valid_sources[0x3c]	3789	1			T2	11		T4	14		T5	1
valid_sources[0x3d]	3872	1			T2	21		T3	58		T4	11
valid_sources[0x3e]	3969	1			T2	36		T4	7		T5	1
valid_sources[0x3f]	4920	1			T2	22		T4	13		T5	3
valid_sources[0x40]	4273	1			T2	39		T4	22		T5	1
valid_sources[0x41]	3504	1			T2	20		T4	7		T5	1
valid_sources[0x42]	4573	1			T2	26		T4	16		T5	5
valid_sources[0x43]	4200	1			T2	20		T4	13		T5	2
valid_sources[0x44]	4707	1			T2	27		T4	20		T8	30
valid_sources[0x45]	3340	1			T2	18		T4	13		T5	3
valid_sources[0x46]	3735	1			T2	7		T3	146		T4	10
valid_sources[0x47]	3623	1			T2	13		T3	284		T4	10
valid_sources[0x48]	3605	1			T2	30		T4	12		T5	4
valid_sources[0x49]	4327	1			T2	31		T3	367		T4	12
valid_sources[0x4a]	4051	1			T2	10		T4	10		T5	5
valid_sources[0x4b]	3263	1			T2	18		T4	13		T8	22
valid_sources[0x4c]	5045	1			T2	29		T4	11		T8	43
valid_sources[0x4d]	4291	1			T2	14		T4	15		T5	2
valid_sources[0x4e]	3819	1			T2	16		T4	12		T5	2
valid_sources[0x4f]	3555	1			T2	28		T4	8		T5	3
valid_sources[0x50]	3406	1			T2	19		T4	6		T8	19
valid_sources[0x51]	3646	1			T2	24		T4	8		T5	1
valid_sources[0x52]	3601	1			T2	6		T4	11		T5	3
valid_sources[0x53]	3426	1			T2	24		T3	2		T4	11
valid_sources[0x54]	3892	1			T2	20		T4	11		T5	1
valid_sources[0x55]	4295	1			T2	16		T4	9		T5	3
valid_sources[0x56]	3316	1			T2	21		T4	16		T5	4
valid_sources[0x57]	5242	1			T2	16		T4	13		T8	34
valid_sources[0x58]	3839	1			T2	12		T4	12		T5	1
valid_sources[0x59]	3426	1			T2	33		T4	14		T8	45
valid_sources[0x5a]	3763	1			T2	15		T4	14		T8	32
valid_sources[0x5b]	3249	1			T2	21		T4	7		T5	1
valid_sources[0x5c]	3499	1			T2	22		T4	8		T5	5
valid_sources[0x5d]	3394	1			T2	9		T4	7		T5	3
valid_sources[0x5e]	4034	1			T2	21		T4	6		T8	55
valid_sources[0x5f]	5682	1			T2	29		T4	9		T5	2
valid_sources[0x60]	4746	1			T2	22		T3	158		T4	11
valid_sources[0x61]	3232	1			T2	24		T4	9		T8	25
valid_sources[0x62]	3729	1			T2	29		T4	7		T5	1
valid_sources[0x63]	3563	1			T2	25		T4	17		T8	45
valid_sources[0x64]	3958	1			T2	21		T3	323		T4	14
valid_sources[0x65]	3935	1			T2	17		T3	70		T4	8
valid_sources[0x66]	3780	1			T2	15		T4	9		T8	30
valid_sources[0x67]	3553	1			T2	38		T4	5		T8	28
valid_sources[0x68]	3678	1			T2	10		T4	19		T5	1
valid_sources[0x69]	3455	1			T2	27		T4	9		T5	5
valid_sources[0x6a]	4383	1			T2	25		T4	12		T5	3
valid_sources[0x6b]	4232	1			T2	30		T4	13		T5	3
valid_sources[0x6c]	3752	1			T2	26		T4	16		T5	2
valid_sources[0x6d]	3401	1			T2	28		T4	17		T5	2
valid_sources[0x6e]	3546	1			T2	17		T4	8		T8	23
valid_sources[0x6f]	5197	1			T2	30		T3	70		T4	5
valid_sources[0x70]	3480	1			T2	28		T3	5		T4	12
valid_sources[0x71]	3356	1			T2	29		T4	12		T8	22
valid_sources[0x72]	3692	1			T2	12		T4	11		T8	47
valid_sources[0x73]	7359	1			T2	31		T4	8		T8	34
valid_sources[0x74]	3155	1			T2	18		T4	13		T5	5
valid_sources[0x75]	4266	1			T2	9		T4	5		T5	3
valid_sources[0x76]	5076	1			T2	4		T4	8		T8	27
valid_sources[0x77]	4162	1			T2	22		T4	9		T5	1
valid_sources[0x78]	3324	1			T2	23		T3	1		T4	14
valid_sources[0x79]	4485	1			T2	18		T4	9		T5	1
valid_sources[0x7a]	3469	1			T2	13		T4	16		T8	19
valid_sources[0x7b]	3451	1			T2	20		T4	16		T8	27
valid_sources[0x7c]	3284	1			T2	13		T3	63		T4	8
valid_sources[0x7d]	3681	1			T2	19		T4	13		T8	44
valid_sources[0x7e]	3794	1			T2	38		T4	14		T5	2
valid_sources[0x7f]	3541	1			T2	24		T4	20		T5	2
valid_sources[0x80]	4375	1			T2	34		T3	1		T4	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

253825

1

T2

1299

T3

1629

T4

740

values[0x0]

all_enables

biggest_size

82146

1

T2

425

T3

448

T4

183

values[0x1]

all_enables

biggest_size

43668

1

T2

208

T3

211

T4

82