Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56386708	9053	0	0
CascadeEffAonToRstPorAboveRise_A	56386708	9053	0	0
CascadeEffAonToRstPorIoAboveFall_A	54129335	9053	0	0
CascadeEffAonToRstPorIoAboveRise_A	54129335	9053	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27065631	9053	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27065631	9053	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13532367	9053	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13532367	9053	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27065318	9053	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27065318	9053	0	0
CascadeLcToLcAboveFall_A	56386708	22566	0	0
CascadeLcToLcAboveRise_A	56386708	22566	0	0
CascadeLcToLcAonAboveFall_A	1709198	22566	0	0
CascadeLcToLcAonAboveRise_A	1709198	22566	0	0
CascadeLcToLcShadowedAboveFall_A	56386708	22566	0	0
CascadeLcToLcShadowedAboveRise_A	56386708	22566	0	0
CascadePorToAonAboveFall_A	1709198	7118	0	0
CascadeSysToSysAboveFall_A	56386708	22566	0	0
CascadeSysToSysAboveRise_A	56386708	22566	0	0
ScanRstToAonRise_A	1709198	211	0	0
StablePorToAonRise_A	1709198	9053	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11982268	22566	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11982268	22566	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11982268	22566	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11982268	22566	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13532367	22566	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13532367	22566	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11982268	22566	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11982268	22566	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11982268	22566	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11982268	22566	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	9053	0	0
T1	24219	8	0	0
T2	277568	33	0	0
T3	206545	47	0	0
T4	91720	21	0	0
T5	12752	2	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	46	0	0
T9	43249	1	0	0
T10	188474	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	9053	0	0
T1	24219	8	0	0
T2	277568	33	0	0
T3	206545	47	0	0
T4	91720	21	0	0
T5	12752	2	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	46	0	0
T9	43249	1	0	0
T10	188474	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54129335	9053	0	0
T1	23235	8	0	0
T2	266433	33	0	0
T3	198256	47	0	0
T4	88033	21	0	0
T5	12238	2	0	0
T6	23384	8	0	0
T7	23347	8	0	0
T8	403194	46	0	0
T9	41518	1	0	0
T10	180975	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54129335	9053	0	0
T1	23235	8	0	0
T2	266433	33	0	0
T3	198256	47	0	0
T4	88033	21	0	0
T5	12238	2	0	0
T6	23384	8	0	0
T7	23347	8	0	0
T8	403194	46	0	0
T9	41518	1	0	0
T10	180975	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065631	9053	0	0
T1	11618	8	0	0
T2	133230	33	0	0
T3	99138	47	0	0
T4	44023	21	0	0
T5	6118	2	0	0
T6	11689	8	0	0
T7	11671	8	0	0
T8	201605	46	0	0
T9	20759	1	0	0
T10	90489	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065631	9053	0	0
T1	11618	8	0	0
T2	133230	33	0	0
T3	99138	47	0	0
T4	44023	21	0	0
T5	6118	2	0	0
T6	11689	8	0	0
T7	11671	8	0	0
T8	201605	46	0	0
T9	20759	1	0	0
T10	90489	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	9053	0	0
T1	5809	8	0	0
T2	66610	33	0	0
T3	49573	47	0	0
T4	22005	21	0	0
T5	3058	2	0	0
T6	5847	8	0	0
T7	5835	8	0	0
T8	100801	46	0	0
T9	10379	1	0	0
T10	45245	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	9053	0	0
T1	5809	8	0	0
T2	66610	33	0	0
T3	49573	47	0	0
T4	22005	21	0	0
T5	3058	2	0	0
T6	5847	8	0	0
T7	5835	8	0	0
T8	100801	46	0	0
T9	10379	1	0	0
T10	45245	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065318	9053	0	0
T1	11614	8	0	0
T2	133210	33	0	0
T3	99146	47	0	0
T4	44021	21	0	0
T5	6120	2	0	0
T6	11690	8	0	0
T7	11674	8	0	0
T8	201617	46	0	0
T9	20759	1	0	0
T10	90495	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065318	9053	0	0
T1	11614	8	0	0
T2	133210	33	0	0
T3	99146	47	0	0
T4	44021	21	0	0
T5	6120	2	0	0
T6	11690	8	0	0
T7	11674	8	0	0
T8	201617	46	0	0
T9	20759	1	0	0
T10	90495	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	22566	0	0
T1	24219	8	0	0
T2	277568	110	0	0
T3	206545	121	0	0
T4	91720	54	0	0
T5	12752	6	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	154	0	0
T9	43249	1	0	0
T10	188474	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	22566	0	0
T1	24219	8	0	0
T2	277568	110	0	0
T3	206545	121	0	0
T4	91720	54	0	0
T5	12752	6	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	154	0	0
T9	43249	1	0	0
T10	188474	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	22566	0	0
T1	729	8	0	0
T2	8481	110	0	0
T3	6317	121	0	0
T4	2789	54	0	0
T5	381	6	0	0
T6	732	8	0	0
T7	731	8	0	0
T8	12708	154	0	0
T9	1296	1	0	0
T10	5670	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	22566	0	0
T1	729	8	0	0
T2	8481	110	0	0
T3	6317	121	0	0
T4	2789	54	0	0
T5	381	6	0	0
T6	732	8	0	0
T7	731	8	0	0
T8	12708	154	0	0
T9	1296	1	0	0
T10	5670	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	22566	0	0
T1	24219	8	0	0
T2	277568	110	0	0
T3	206545	121	0	0
T4	91720	54	0	0
T5	12752	6	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	154	0	0
T9	43249	1	0	0
T10	188474	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	22566	0	0
T1	24219	8	0	0
T2	277568	110	0	0
T3	206545	121	0	0
T4	91720	54	0	0
T5	12752	6	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	154	0	0
T9	43249	1	0	0
T10	188474	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	7118	0	0
T1	729	8	0	0
T2	8481	16	0	0
T3	6317	21	0	0
T4	2789	10	0	0
T5	381	1	0	0
T6	732	8	0	0
T7	731	8	0	0
T8	12708	22	0	0
T9	1296	1	0	0
T10	5670	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	22566	0	0
T1	24219	8	0	0
T2	277568	110	0	0
T3	206545	121	0	0
T4	91720	54	0	0
T5	12752	6	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	154	0	0
T9	43249	1	0	0
T10	188474	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56386708	22566	0	0
T1	24219	8	0	0
T2	277568	110	0	0
T3	206545	121	0	0
T4	91720	54	0	0
T5	12752	6	0	0
T6	24354	8	0	0
T7	24341	8	0	0
T8	419989	154	0	0
T9	43249	1	0	0
T10	188474	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	211	0	0
T2	8481	2	0	0
T3	6317	4	0	0
T4	2789	1	0	0
T5	381	0	0	0
T6	732	0	0	0
T7	731	0	0	0
T8	12708	3	0	0
T9	1296	0	0	0
T10	5670	0	0	0
T11	431	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	3	0	0
T49	0	1	0	0
T81	0	1	0	0
T86	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	9053	0	0
T1	729	8	0	0
T2	8481	33	0	0
T3	6317	47	0	0
T4	2789	21	0	0
T5	381	2	0	0
T6	732	8	0	0
T7	731	8	0	0
T8	12708	46	0	0
T9	1296	1	0	0
T10	5670	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	22566	0	0
T1	5809	8	0	0
T2	66610	110	0	0
T3	49573	121	0	0
T4	22005	54	0	0
T5	3058	6	0	0
T6	5847	8	0	0
T7	5835	8	0	0
T8	100801	154	0	0
T9	10379	1	0	0
T10	45245	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	22566	0	0
T1	5809	8	0	0
T2	66610	110	0	0
T3	49573	121	0	0
T4	22005	54	0	0
T5	3058	6	0	0
T6	5847	8	0	0
T7	5835	8	0	0
T8	100801	154	0	0
T9	10379	1	0	0
T10	45245	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11982268	22566	0	0
T1	5073	8	0	0
T2	56267	110	0	0
T3	38772	121	0	0
T4	17220	54	0	0
T5	2771	6	0	0
T6	5108	8	0	0
T7	5676	8	0	0
T8	88665	154	0	0
T9	10336	1	0	0
T10	42092	102	0	0