Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T14
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T14
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T14
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T62
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13532367	14460	0	0
gen_assertions[0].RstEnOn_A	13532367	1119	0	0
gen_assertions[0].RstNOff_A	13532367	14460	0	0
gen_assertions[0].RstNOn_A	13532367	1119	0	0
gen_assertions[1].RstEnOff_A	54129335	13118	0	0
gen_assertions[1].RstEnOn_A	54129335	1064	0	0
gen_assertions[1].RstNOff_A	54129335	13118	0	0
gen_assertions[1].RstNOn_A	54129335	1064	0	0
gen_assertions[2].RstEnOff_A	27065631	13137	0	0
gen_assertions[2].RstEnOn_A	27065631	1035	0	0
gen_assertions[2].RstNOff_A	27065631	13137	0	0
gen_assertions[2].RstNOn_A	27065631	1035	0	0
gen_assertions[3].RstEnOff_A	27065318	13235	0	0
gen_assertions[3].RstEnOn_A	27065318	1129	0	0
gen_assertions[3].RstNOff_A	27065318	13235	0	0
gen_assertions[3].RstNOn_A	27065318	1129	0	0
gen_assertions[4].RstEnOff_A	1709198	22417	0	0
gen_assertions[4].RstEnOn_A	1709198	1190	0	0
gen_assertions[4].RstNOff_A	1709198	22417	0	0
gen_assertions[4].RstNOn_A	1709198	1190	0	0
gen_assertions[5].RstEnOff_A	13532367	14691	0	0
gen_assertions[5].RstEnOn_A	13532367	1210	0	0
gen_assertions[5].RstNOff_A	13532367	14691	0	0
gen_assertions[5].RstNOn_A	13532367	1210	0	0
gen_assertions[6].RstEnOff_A	13532367	14727	0	0
gen_assertions[6].RstEnOn_A	13532367	1261	0	0
gen_assertions[6].RstNOff_A	13532367	14727	0	0
gen_assertions[6].RstNOn_A	13532367	1261	0	0
gen_assertions[7].RstEnOff_A	13532367	14766	0	0
gen_assertions[7].RstEnOn_A	13532367	1290	0	0
gen_assertions[7].RstNOff_A	13532367	14766	0	0
gen_assertions[7].RstNOn_A	13532367	1290	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14460	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	4	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	126	0	0
T9	10379	2	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1119	0	0
T8	100801	22	0	0
T9	10379	2	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	7	0	0
T31	0	1	0	0
T40	5850	4	0	0
T41	3518	0	0	0
T42	3907	5	0	0
T57	0	5	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14460	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	4	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	126	0	0
T9	10379	2	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1119	0	0
T8	100801	22	0	0
T9	10379	2	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	7	0	0
T31	0	1	0	0
T40	5850	4	0	0
T41	3518	0	0	0
T42	3907	5	0	0
T57	0	5	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54129335	13118	0	0
T2	266433	73	0	0
T3	198256	68	0	0
T4	88033	31	0	0
T5	12238	3	0	0
T6	23384	0	0	0
T7	23347	0	0	0
T8	403194	116	0	0
T9	41518	4	0	0
T10	180975	69	0	0
T11	13858	4	0	0
T12	0	63	0	0
T13	0	36	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54129335	1064	0	0
T8	403194	19	0	0
T9	41518	4	0	0
T10	180975	0	0	0
T11	13858	0	0	0
T12	117042	0	0	0
T13	91159	0	0	0
T14	14272	6	0	0
T40	23404	0	0	0
T41	14080	0	0	0
T42	15635	7	0	0
T60	0	11	0	0
T62	0	4	0	0
T63	0	5	0	0
T85	0	1	0	0
T86	0	50	0	0
T87	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54129335	13118	0	0
T2	266433	73	0	0
T3	198256	68	0	0
T4	88033	31	0	0
T5	12238	3	0	0
T6	23384	0	0	0
T7	23347	0	0	0
T8	403194	116	0	0
T9	41518	4	0	0
T10	180975	69	0	0
T11	13858	4	0	0
T12	0	63	0	0
T13	0	36	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54129335	1064	0	0
T8	403194	19	0	0
T9	41518	4	0	0
T10	180975	0	0	0
T11	13858	0	0	0
T12	117042	0	0	0
T13	91159	0	0	0
T14	14272	6	0	0
T40	23404	0	0	0
T41	14080	0	0	0
T42	15635	7	0	0
T60	0	11	0	0
T62	0	4	0	0
T63	0	5	0	0
T85	0	1	0	0
T86	0	50	0	0
T87	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065631	13137	0	0
T2	133230	73	0	0
T3	99138	68	0	0
T4	44023	31	0	0
T5	6118	3	0	0
T6	11689	0	0	0
T7	11671	0	0	0
T8	201605	113	0	0
T9	20759	6	0	0
T10	90489	69	0	0
T11	6927	4	0	0
T12	0	63	0	0
T13	0	36	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065631	1035	0	0
T8	201605	18	0	0
T9	20759	6	0	0
T10	90489	0	0	0
T11	6927	0	0	0
T12	58527	0	0	0
T13	45581	0	0	0
T14	7137	2	0	0
T40	11702	0	0	0
T41	7038	0	0	0
T42	7818	0	0	0
T60	0	11	0	0
T61	0	1	0	0
T62	0	5	0	0
T63	0	6	0	0
T85	0	3	0	0
T86	0	43	0	0
T87	0	12	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065631	13137	0	0
T2	133230	73	0	0
T3	99138	68	0	0
T4	44023	31	0	0
T5	6118	3	0	0
T6	11689	0	0	0
T7	11671	0	0	0
T8	201605	113	0	0
T9	20759	6	0	0
T10	90489	69	0	0
T11	6927	4	0	0
T12	0	63	0	0
T13	0	36	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065631	1035	0	0
T8	201605	18	0	0
T9	20759	6	0	0
T10	90489	0	0	0
T11	6927	0	0	0
T12	58527	0	0	0
T13	45581	0	0	0
T14	7137	2	0	0
T40	11702	0	0	0
T41	7038	0	0	0
T42	7818	0	0	0
T60	0	11	0	0
T61	0	1	0	0
T62	0	5	0	0
T63	0	6	0	0
T85	0	3	0	0
T86	0	43	0	0
T87	0	12	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065318	13235	0	0
T2	133210	73	0	0
T3	99146	68	0	0
T4	44021	31	0	0
T5	6120	3	0	0
T6	11690	0	0	0
T7	11674	0	0	0
T8	201617	111	0	0
T9	20759	7	0	0
T10	90495	69	0	0
T11	6930	4	0	0
T12	0	63	0	0
T13	0	36	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065318	1129	0	0
T8	201617	15	0	0
T9	20759	7	0	0
T10	90495	0	0	0
T11	6930	0	0	0
T12	58514	0	0	0
T13	45560	0	0	0
T14	7136	0	0	0
T31	0	1	0	0
T40	11702	0	0	0
T41	7041	0	0	0
T42	7818	0	0	0
T60	0	12	0	0
T61	0	1	0	0
T62	0	6	0	0
T63	0	8	0	0
T85	0	4	0	0
T86	0	53	0	0
T87	0	13	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065318	13235	0	0
T2	133210	73	0	0
T3	99146	68	0	0
T4	44021	31	0	0
T5	6120	3	0	0
T6	11690	0	0	0
T7	11674	0	0	0
T8	201617	111	0	0
T9	20759	7	0	0
T10	90495	69	0	0
T11	6930	4	0	0
T12	0	63	0	0
T13	0	36	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27065318	1129	0	0
T8	201617	15	0	0
T9	20759	7	0	0
T10	90495	0	0	0
T11	6930	0	0	0
T12	58514	0	0	0
T13	45560	0	0	0
T14	7136	0	0	0
T31	0	1	0	0
T40	11702	0	0	0
T41	7041	0	0	0
T42	7818	0	0	0
T60	0	12	0	0
T61	0	1	0	0
T62	0	6	0	0
T63	0	8	0	0
T85	0	4	0	0
T86	0	53	0	0
T87	0	13	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	22417	0	0
T1	729	3	0	0
T2	8481	108	0	0
T3	6317	118	0	0
T4	2789	53	0	0
T5	381	6	0	0
T6	732	3	0	0
T7	731	3	0	0
T8	12708	172	0	0
T9	1296	9	0	0
T10	5670	91	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	1190	0	0
T8	12708	21	0	0
T9	1296	8	0	0
T10	5670	0	0	0
T11	431	0	0	0
T12	3672	0	0	0
T13	2905	0	0	0
T14	444	0	0	0
T40	730	0	0	0
T41	439	0	0	0
T42	487	0	0	0
T60	0	13	0	0
T62	0	7	0	0
T63	0	7	0	0
T85	0	5	0	0
T86	0	51	0	0
T87	0	12	0	0
T88	0	5	0	0
T89	0	7	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	22417	0	0
T1	729	3	0	0
T2	8481	108	0	0
T3	6317	118	0	0
T4	2789	53	0	0
T5	381	6	0	0
T6	732	3	0	0
T7	731	3	0	0
T8	12708	172	0	0
T9	1296	9	0	0
T10	5670	91	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1709198	1190	0	0
T8	12708	21	0	0
T9	1296	8	0	0
T10	5670	0	0	0
T11	431	0	0	0
T12	3672	0	0	0
T13	2905	0	0	0
T14	444	0	0	0
T40	730	0	0	0
T41	439	0	0	0
T42	487	0	0	0
T60	0	13	0	0
T62	0	7	0	0
T63	0	7	0	0
T85	0	5	0	0
T86	0	51	0	0
T87	0	12	0	0
T88	0	5	0	0
T89	0	7	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14691	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	4	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	125	0	0
T9	10379	8	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1210	0	0
T8	100801	19	0	0
T9	10379	8	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	0	0	0
T40	5850	0	0	0
T41	3518	0	0	0
T42	3907	0	0	0
T60	0	15	0	0
T61	0	1	0	0
T62	0	6	0	0
T63	0	10	0	0
T85	0	5	0	0
T86	0	54	0	0
T87	0	8	0	0
T88	0	5	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14691	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	4	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	125	0	0
T9	10379	8	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1210	0	0
T8	100801	19	0	0
T9	10379	8	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	0	0	0
T40	5850	0	0	0
T41	3518	0	0	0
T42	3907	0	0	0
T60	0	15	0	0
T61	0	1	0	0
T62	0	6	0	0
T63	0	10	0	0
T85	0	5	0	0
T86	0	54	0	0
T87	0	8	0	0
T88	0	5	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14727	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	5	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	125	0	0
T9	10379	9	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1261	0	0
T5	3058	1	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	20	0	0
T9	10379	9	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	0	0	0
T60	0	9	0	0
T61	0	1	0	0
T62	0	8	0	0
T63	0	9	0	0
T85	0	6	0	0
T86	0	44	0	0
T87	0	12	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14727	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	5	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	125	0	0
T9	10379	9	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1261	0	0
T5	3058	1	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	20	0	0
T9	10379	9	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	0	0	0
T60	0	9	0	0
T61	0	1	0	0
T62	0	8	0	0
T63	0	9	0	0
T85	0	6	0	0
T86	0	44	0	0
T87	0	12	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14766	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	4	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	124	0	0
T9	10379	10	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1290	0	0
T8	100801	17	0	0
T9	10379	10	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	0	0	0
T40	5850	0	0	0
T41	3518	0	0	0
T42	3907	0	0	0
T60	0	13	0	0
T62	0	9	0	0
T63	0	10	0	0
T85	0	7	0	0
T86	0	49	0	0
T87	0	11	0	0
T88	0	4	0	0
T89	0	9	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	14766	0	0
T2	66610	77	0	0
T3	49573	74	0	0
T4	22005	33	0	0
T5	3058	4	0	0
T6	5847	0	0	0
T7	5835	0	0	0
T8	100801	124	0	0
T9	10379	10	0	0
T10	45245	75	0	0
T11	3464	4	0	0
T12	0	75	0	0
T13	0	38	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13532367	1290	0	0
T8	100801	17	0	0
T9	10379	10	0	0
T10	45245	0	0	0
T11	3464	0	0	0
T12	29264	0	0	0
T13	22794	0	0	0
T14	3567	0	0	0
T40	5850	0	0	0
T41	3518	0	0	0
T42	3907	0	0	0
T60	0	13	0	0
T62	0	9	0	0
T63	0	10	0	0
T85	0	7	0	0
T86	0	49	0	0
T87	0	11	0	0
T88	0	4	0	0
T89	0	9	0	0