Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12664934	6800	0	0
alert_regwen_rd_A	12664934	4676	0	0
cpu_regwen_rd_A	12664934	4580	0	0
sw_rst_ctrl_n_0_rd_A	12664934	9405	0	0
sw_rst_ctrl_n_1_rd_A	12664934	9263	0	0
sw_rst_ctrl_n_2_rd_A	12664934	9306	0	0
sw_rst_ctrl_n_3_rd_A	12664934	9269	0	0
sw_rst_ctrl_n_4_rd_A	12664934	9274	0	0
sw_rst_ctrl_n_5_rd_A	12664934	9306	0	0
sw_rst_ctrl_n_6_rd_A	12664934	9066	0	0
sw_rst_ctrl_n_7_rd_A	12664934	9498	0	0
sw_rst_regwen_0_rd_A	12664934	4881	0	0
sw_rst_regwen_1_rd_A	12664934	5054	0	0
sw_rst_regwen_2_rd_A	12664934	5024	0	0
sw_rst_regwen_3_rd_A	12664934	5152	0	0
sw_rst_regwen_4_rd_A	12664934	5085	0	0
sw_rst_regwen_5_rd_A	12664934	5058	0	0
sw_rst_regwen_6_rd_A	12664934	4934	0	0
sw_rst_regwen_7_rd_A	12664934	5041	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	6800	0	0
T64	19962	3	0	0
T67	3224	7	0	0
T69	5024	128	0	0
T70	2522	143	0	0
T71	3990	93	0	0
T93	6169	273	0	0
T94	2244	5	0	0
T95	4250	111	0	0
T97	11515	2	0	0
T98	11079	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	4676	0	0
T17	1986	0	0	0
T18	3751	0	0	0
T26	31117	25	0	0
T27	26303	0	0	0
T28	40628	36	0	0
T29	3981	0	0	0
T30	14404	0	0	0
T31	4377	0	0	0
T60	181329	223	0	0
T85	6356	0	0	0
T86	0	154	0	0
T87	0	72	0	0
T103	0	49	0	0
T125	0	17	0	0
T126	0	57	0	0
T127	0	32	0	0
T128	0	75	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	4580	0	0
T17	1986	0	0	0
T18	3751	0	0	0
T26	31117	13	0	0
T27	26303	0	0	0
T28	40628	47	0	0
T29	3981	0	0	0
T30	14404	0	0	0
T31	4377	0	0	0
T60	181329	244	0	0
T85	6356	0	0	0
T86	0	171	0	0
T87	0	98	0	0
T103	0	52	0	0
T125	0	40	0	0
T126	0	54	0	0
T127	0	62	0	0
T128	0	79	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9405	0	0
T9	10336	167	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	20	0	0
T28	0	59	0	0
T40	4752	66	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	429	0	0
T63	0	60	0	0
T82	0	44	0	0
T86	0	610	0	0
T87	0	152	0	0
T103	0	57	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9263	0	0
T9	10336	146	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	27	0	0
T28	0	36	0	0
T40	4752	56	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	379	0	0
T63	0	93	0	0
T82	0	41	0	0
T86	0	564	0	0
T87	0	148	0	0
T103	0	61	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9306	0	0
T9	10336	179	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	26	0	0
T28	0	36	0	0
T40	4752	46	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	395	0	0
T63	0	99	0	0
T82	0	40	0	0
T86	0	553	0	0
T87	0	149	0	0
T103	0	56	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9269	0	0
T9	10336	141	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	14	0	0
T28	0	37	0	0
T40	4752	58	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	419	0	0
T63	0	102	0	0
T82	0	54	0	0
T86	0	528	0	0
T87	0	148	0	0
T103	0	45	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9274	0	0
T9	10336	145	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	37	0	0
T28	0	68	0	0
T40	4752	58	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	406	0	0
T63	0	128	0	0
T82	0	62	0	0
T86	0	522	0	0
T87	0	180	0	0
T103	0	43	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9306	0	0
T9	10336	138	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	47	0	0
T28	0	58	0	0
T40	4752	40	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	330	0	0
T63	0	150	0	0
T82	0	41	0	0
T86	0	548	0	0
T87	0	150	0	0
T103	0	51	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9066	0	0
T9	10336	155	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	9	0	0
T28	0	63	0	0
T40	4752	69	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	400	0	0
T63	0	91	0	0
T82	0	55	0	0
T86	0	498	0	0
T87	0	114	0	0
T103	0	54	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	9498	0	0
T9	10336	137	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	26	0	0
T28	0	48	0	0
T40	4752	66	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	421	0	0
T63	0	129	0	0
T82	0	59	0	0
T86	0	521	0	0
T87	0	163	0	0
T103	0	64	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	4881	0	0
T9	10336	43	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	49	0	0
T28	0	54	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	228	0	0
T63	0	43	0	0
T86	0	131	0	0
T87	0	118	0	0
T103	0	65	0	0
T125	0	31	0	0
T129	0	19	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	5054	0	0
T9	10336	45	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	37	0	0
T28	0	27	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	201	0	0
T63	0	11	0	0
T86	0	140	0	0
T87	0	134	0	0
T103	0	58	0	0
T125	0	28	0	0
T129	0	39	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	5024	0	0
T9	10336	44	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	34	0	0
T28	0	74	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	193	0	0
T63	0	21	0	0
T86	0	149	0	0
T87	0	124	0	0
T103	0	50	0	0
T125	0	24	0	0
T129	0	29	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	5152	0	0
T9	10336	34	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	23	0	0
T28	0	61	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	244	0	0
T63	0	46	0	0
T86	0	110	0	0
T87	0	90	0	0
T103	0	87	0	0
T125	0	25	0	0
T129	0	35	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	5085	0	0
T9	10336	39	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	29	0	0
T28	0	48	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	235	0	0
T63	0	24	0	0
T86	0	133	0	0
T87	0	104	0	0
T103	0	41	0	0
T125	0	31	0	0
T129	0	28	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	5058	0	0
T9	10336	31	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	26	0	0
T28	0	44	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	225	0	0
T63	0	26	0	0
T86	0	121	0	0
T87	0	104	0	0
T103	0	67	0	0
T125	0	20	0	0
T129	0	42	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	4934	0	0
T9	10336	24	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	30	0	0
T28	0	23	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	269	0	0
T63	0	25	0	0
T86	0	145	0	0
T87	0	109	0	0
T103	0	59	0	0
T125	0	36	0	0
T129	0	23	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12664934	5041	0	0
T9	10336	26	0	0
T10	42092	0	0	0
T11	3318	0	0	0
T12	26237	0	0	0
T13	18049	0	0	0
T14	2512	0	0	0
T26	0	18	0	0
T28	0	19	0	0
T40	4752	0	0	0
T41	3133	0	0	0
T42	2496	0	0	0
T43	5475	0	0	0
T60	0	254	0	0
T63	0	19	0	0
T86	0	159	0	0
T87	0	84	0	0
T103	0	63	0	0
T125	0	33	0	0
T129	0	35	0	0