Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	656611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

395687

1

T1

62

T2

96

T4

68

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	561610	1			T1	99		T2	136		T3	1
values[0x0]	244873	1			T1	64		T2	72		T4	51
values[0x1]	245815	1			T1	49		T2	69		T4	62

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	550704	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

501594

1

T1

82

T2

130

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4096	1			T2	1		T4	3		T5	5
valid_sources[0x01]	3101	1			T8	2		T20	22		T62	6
valid_sources[0x02]	4114	1			T2	1		T6	1		T12	1
valid_sources[0x03]	3275	1			T2	1		T5	1		T6	1
valid_sources[0x04]	4657	1			T6	1		T12	2		T20	3
valid_sources[0x05]	4569	1			T2	2		T5	1		T6	2
valid_sources[0x06]	3540	1			T2	2		T4	2		T5	6
valid_sources[0x07]	3648	1			T2	1		T62	5		T21	11
valid_sources[0x08]	5155	1			T2	1		T4	2		T5	4
valid_sources[0x09]	4006	1			T2	4		T20	1		T62	1
valid_sources[0x0a]	5725	1			T2	2		T6	3		T20	13
valid_sources[0x0b]	3411	1			T2	4		T4	2		T5	6
valid_sources[0x0c]	3661	1			T5	1		T20	11		T62	4
valid_sources[0x0d]	3378	1			T2	2		T20	22		T62	11
valid_sources[0x0e]	4095	1			T1	1		T2	1		T4	1
valid_sources[0x0f]	3618	1			T2	2		T5	1		T6	1
valid_sources[0x10]	4485	1			T2	1		T5	4		T6	4
valid_sources[0x11]	4033	1			T2	1		T5	12		T6	2
valid_sources[0x12]	4036	1			T2	4		T4	7		T6	1
valid_sources[0x13]	3302	1			T2	1		T4	1		T5	2
valid_sources[0x14]	4502	1			T2	1		T5	2		T6	3
valid_sources[0x15]	3061	1			T2	2		T5	2		T6	1
valid_sources[0x16]	3070	1			T5	1		T62	17		T21	3
valid_sources[0x17]	5065	1			T2	1		T5	2		T6	1
valid_sources[0x18]	3871	1			T1	24		T2	1		T4	7
valid_sources[0x19]	3352	1			T2	2		T5	3		T6	3
valid_sources[0x1a]	3608	1			T2	1		T4	13		T6	2
valid_sources[0x1b]	3232	1			T1	1		T2	1		T5	1
valid_sources[0x1c]	3039	1			T2	1		T5	5		T6	3
valid_sources[0x1d]	6368	1			T8	6		T20	6		T62	1
valid_sources[0x1e]	4405	1			T5	5		T6	2		T62	10
valid_sources[0x1f]	4130	1			T2	1		T21	11		T90	14
valid_sources[0x20]	3941	1			T2	4		T5	5		T6	2
valid_sources[0x21]	3807	1			T5	1		T6	3		T12	4
valid_sources[0x22]	7495	1			T5	3		T20	14		T62	2
valid_sources[0x23]	3520	1			T5	3		T8	2		T12	1
valid_sources[0x24]	4146	1			T5	6		T6	1		T20	32
valid_sources[0x25]	3410	1			T4	1		T6	1		T8	1
valid_sources[0x26]	3949	1			T2	1		T5	1		T6	7
valid_sources[0x27]	4305	1			T6	1		T20	6		T62	5
valid_sources[0x28]	7502	1			T2	5		T5	7		T20	57
valid_sources[0x29]	3814	1			T2	1		T5	14		T6	2
valid_sources[0x2a]	7161	1			T2	1		T12	4		T20	23
valid_sources[0x2b]	5075	1			T2	2		T5	1		T6	1
valid_sources[0x2c]	5374	1			T2	2		T5	2		T6	2
valid_sources[0x2d]	6469	1			T5	1		T6	1		T12	1
valid_sources[0x2e]	3607	1			T6	1		T8	8		T12	1
valid_sources[0x2f]	3907	1			T2	1		T8	12		T12	2
valid_sources[0x30]	4379	1			T6	3		T20	36		T62	4
valid_sources[0x31]	3933	1			T1	6		T2	4		T5	6
valid_sources[0x32]	3509	1			T2	3		T20	28		T62	1
valid_sources[0x33]	3742	1			T2	1		T5	2		T12	1
valid_sources[0x34]	4924	1			T2	1		T5	1		T6	3
valid_sources[0x35]	4186	1			T1	20		T6	5		T20	9
valid_sources[0x36]	5006	1			T2	1		T6	1		T8	1
valid_sources[0x37]	4928	1			T5	1		T6	4		T8	1
valid_sources[0x38]	4914	1			T2	1		T5	1		T8	4
valid_sources[0x39]	3598	1			T5	1		T6	3		T20	9
valid_sources[0x3a]	3575	1			T2	2		T4	1		T6	1
valid_sources[0x3b]	4647	1			T2	2		T4	1		T5	5
valid_sources[0x3c]	3251	1			T6	5		T12	3		T20	7
valid_sources[0x3d]	3612	1			T2	1		T4	1		T20	29
valid_sources[0x3e]	3514	1			T2	2		T6	1		T8	3
valid_sources[0x3f]	4760	1			T1	7		T2	1		T5	1
valid_sources[0x40]	4417	1			T1	17		T2	1		T6	5
valid_sources[0x41]	4471	1			T2	1		T6	3		T12	2
valid_sources[0x42]	3551	1			T4	1		T6	2		T62	1
valid_sources[0x43]	3801	1			T2	2		T4	1		T5	7
valid_sources[0x44]	3556	1			T2	1		T4	1		T6	1
valid_sources[0x45]	3570	1			T5	4		T6	1		T12	2
valid_sources[0x46]	3189	1			T2	2		T5	2		T6	5
valid_sources[0x47]	3835	1			T2	1		T4	2		T5	3
valid_sources[0x48]	8388	1			T1	5		T2	1		T4	2
valid_sources[0x49]	3818	1			T2	2		T5	1		T6	1
valid_sources[0x4a]	5062	1			T2	5		T4	3		T6	5
valid_sources[0x4b]	5772	1			T2	1		T4	3		T20	6
valid_sources[0x4c]	3744	1			T2	2		T4	2		T6	2
valid_sources[0x4d]	3984	1			T2	1		T6	3		T20	17
valid_sources[0x4e]	3354	1			T2	2		T5	8		T6	2
valid_sources[0x4f]	3688	1			T4	2		T5	2		T12	3
valid_sources[0x50]	4864	1			T2	4		T5	2		T6	1
valid_sources[0x51]	4280	1			T2	3		T5	2		T8	4
valid_sources[0x52]	3672	1			T2	4		T4	2		T5	1
valid_sources[0x53]	4205	1			T2	2		T6	4		T20	33
valid_sources[0x54]	3872	1			T2	1		T4	3		T20	39
valid_sources[0x55]	3244	1			T1	18		T2	2		T8	12
valid_sources[0x56]	3806	1			T1	4		T2	1		T4	4
valid_sources[0x57]	3330	1			T2	1		T12	2		T62	1
valid_sources[0x58]	4060	1			T2	1		T5	8		T6	1
valid_sources[0x59]	3857	1			T4	1		T5	3		T6	2
valid_sources[0x5a]	3974	1			T2	1		T5	1		T6	1
valid_sources[0x5b]	3356	1			T2	1		T4	1		T20	2
valid_sources[0x5c]	4037	1			T4	2		T5	6		T6	1
valid_sources[0x5d]	4566	1			T5	1		T12	1		T20	23
valid_sources[0x5e]	3726	1			T2	2		T4	1		T20	4
valid_sources[0x5f]	4624	1			T2	1		T5	1		T20	7
valid_sources[0x60]	3838	1			T1	3		T2	2		T6	1
valid_sources[0x61]	3992	1			T6	1		T12	2		T20	37
valid_sources[0x62]	4506	1			T1	3		T2	1		T5	2
valid_sources[0x63]	3662	1			T2	1		T5	3		T6	1
valid_sources[0x64]	6047	1			T2	1		T4	1		T5	1
valid_sources[0x65]	3868	1			T2	2		T6	1		T12	8
valid_sources[0x66]	4067	1			T2	3		T6	1		T8	4
valid_sources[0x67]	3389	1			T2	2		T5	2		T6	2
valid_sources[0x68]	3224	1			T2	1		T5	5		T12	1
valid_sources[0x69]	4036	1			T4	4		T8	2		T12	3
valid_sources[0x6a]	4031	1			T5	8		T12	1		T62	3
valid_sources[0x6b]	4059	1			T2	3		T5	3		T6	3
valid_sources[0x6c]	5262	1			T2	3		T4	2		T6	1
valid_sources[0x6d]	3422	1			T2	1		T6	2		T62	1
valid_sources[0x6e]	3738	1			T5	6		T6	4		T62	7
valid_sources[0x6f]	4053	1			T2	1		T4	7		T6	1
valid_sources[0x70]	4492	1			T5	2		T6	3		T20	11
valid_sources[0x71]	5007	1			T1	21		T2	1		T5	1
valid_sources[0x72]	3359	1			T1	8		T2	1		T4	4
valid_sources[0x73]	3889	1			T5	4		T6	1		T20	4
valid_sources[0x74]	3206	1			T1	35		T2	1		T4	3
valid_sources[0x75]	3787	1			T2	1		T4	6		T12	2
valid_sources[0x76]	3655	1			T2	2		T6	3		T12	1
valid_sources[0x77]	2835	1			T6	2		T8	7		T12	1
valid_sources[0x78]	7261	1			T2	1		T5	3		T8	5
valid_sources[0x79]	6689	1			T2	1		T6	3		T8	7
valid_sources[0x7a]	3271	1			T2	1		T5	1		T20	44
valid_sources[0x7b]	3523	1			T2	1		T4	3		T12	1
valid_sources[0x7c]	3993	1			T4	3		T6	1		T20	9
valid_sources[0x7d]	4183	1			T2	4		T6	2		T20	2
valid_sources[0x7e]	3639	1			T2	3		T5	1		T12	3
valid_sources[0x7f]	3947	1			T6	3		T12	6		T62	1
valid_sources[0x80]	3239	1			T2	1		T6	4		T62	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

263965

1

T1

39

T2

54

T4

44

values[0x0]

all_enables

biggest_size

85738

1

T1

19

T2

25

T4

13

values[0x1]

all_enables

biggest_size

45984

1

T1

4

T2

17

T4

11