Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12723547	13978	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12723547	128810	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12723547	7744803	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12723547	205004	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12723547	13978	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12723547	128810	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12723547	7744803	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12723547	205004	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	13978	0	0
T1	3103	4	0	0
T2	3821	15	0	0
T3	2224	0	0	0
T4	3963	4	0	0
T5	2601	20	0	0
T6	2612	19	0	0
T7	5053	0	0	0
T8	2706	4	0	0
T9	5494	0	0	0
T10	5092	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T22	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	128810	0	0
T1	3103	38	0	0
T2	3821	135	0	0
T3	2224	0	0	0
T4	3963	37	0	0
T5	2601	180	0	0
T6	2612	171	0	0
T7	5053	0	0	0
T8	2706	37	0	0
T9	5494	0	0	0
T10	5092	0	0	0
T12	0	144	0	0
T20	0	247	0	0
T21	0	324	0	0
T22	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	7744803	0	0
T1	3103	2099	0	0
T2	3821	2926	0	0
T3	2224	789	0	0
T4	3963	3016	0	0
T5	2601	1687	0	0
T6	2612	1725	0	0
T7	5053	857	0	0
T8	2706	1729	0	0
T9	5494	595	0	0
T10	5092	564	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	205004	0	0
T1	3103	52	0	0
T2	3821	244	0	0
T3	2224	0	0	0
T4	3963	62	0	0
T5	2601	287	0	0
T6	2612	287	0	0
T7	5053	0	0	0
T8	2706	57	0	0
T9	5494	0	0	0
T10	5092	0	0	0
T12	0	257	0	0
T20	0	381	0	0
T21	0	519	0	0
T22	0	57	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	13978	0	0
T1	3103	4	0	0
T2	3821	15	0	0
T3	2224	0	0	0
T4	3963	4	0	0
T5	2601	20	0	0
T6	2612	19	0	0
T7	5053	0	0	0
T8	2706	4	0	0
T9	5494	0	0	0
T10	5092	0	0	0
T12	0	16	0	0
T20	0	27	0	0
T21	0	35	0	0
T22	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	128810	0	0
T1	3103	38	0	0
T2	3821	135	0	0
T3	2224	0	0	0
T4	3963	37	0	0
T5	2601	180	0	0
T6	2612	171	0	0
T7	5053	0	0	0
T8	2706	37	0	0
T9	5494	0	0	0
T10	5092	0	0	0
T12	0	144	0	0
T20	0	247	0	0
T21	0	324	0	0
T22	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	7744803	0	0
T1	3103	2099	0	0
T2	3821	2926	0	0
T3	2224	789	0	0
T4	3963	3016	0	0
T5	2601	1687	0	0
T6	2612	1725	0	0
T7	5053	857	0	0
T8	2706	1729	0	0
T9	5494	595	0	0
T10	5092	564	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	205004	0	0
T1	3103	52	0	0
T2	3821	244	0	0
T3	2224	0	0	0
T4	3963	62	0	0
T5	2601	287	0	0
T6	2612	287	0	0
T7	5053	0	0	0
T8	2706	57	0	0
T9	5494	0	0	0
T10	5092	0	0	0
T12	0	257	0	0
T20	0	381	0	0
T21	0	519	0	0
T22	0	57	0	0