Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T8
0	1	Covered	T1,T8,T20
1	0	Covered	T20,T21,T90

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	59730137	9314	0	0
CascadeEffAonToRstPorAboveRise_A	59730137	9314	0	0
CascadeEffAonToRstPorIoAboveFall_A	57339003	9314	0	0
CascadeEffAonToRstPorIoAboveRise_A	57339003	9314	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	28670712	9314	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	28670712	9314	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	14335077	9314	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	14335077	9314	0	0
CascadeEffAonToRstPorUcbAboveFall_A	28670751	9314	0	0
CascadeEffAonToRstPorUcbAboveRise_A	28670751	9314	0	0
CascadeLcToLcAboveFall_A	59730137	23292	0	0
CascadeLcToLcAboveRise_A	59730137	23292	0	0
CascadeLcToLcAonAboveFall_A	1809921	23292	0	0
CascadeLcToLcAonAboveRise_A	1809921	23292	0	0
CascadeLcToLcShadowedAboveFall_A	59730137	23292	0	0
CascadeLcToLcShadowedAboveRise_A	59730137	23292	0	0
CascadePorToAonAboveFall_A	1809921	7267	0	0
CascadeSysToSysAboveFall_A	59730137	23292	0	0
CascadeSysToSysAboveRise_A	59730137	23292	0	0
ScanRstToAonRise_A	1809921	237	0	0
StablePorToAonRise_A	1809921	9314	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12723547	23292	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12723547	23292	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12723547	23292	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12723547	23292	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	14335077	23292	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	14335077	23292	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12723547	23292	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12723547	23292	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12723547	23292	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12723547	23292	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	9314	0	0
T1	13522	2	0	0
T2	20042	1	0	0
T3	9749	2	0	0
T4	18119	2	0	0
T5	17076	1	0	0
T6	16783	1	0	0
T7	21434	2	0	0
T8	12283	2	0	0
T9	24365	8	0	0
T10	24296	8	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	9314	0	0
T1	13522	2	0	0
T2	20042	1	0	0
T3	9749	2	0	0
T4	18119	2	0	0
T5	17076	1	0	0
T6	16783	1	0	0
T7	21434	2	0	0
T8	12283	2	0	0
T9	24365	8	0	0
T10	24296	8	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57339003	9314	0	0
T1	12984	2	0	0
T2	19240	1	0	0
T3	9358	2	0	0
T4	17400	2	0	0
T5	16392	1	0	0
T6	16111	1	0	0
T7	20575	2	0	0
T8	11793	2	0	0
T9	23394	8	0	0
T10	23320	8	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57339003	9314	0	0
T1	12984	2	0	0
T2	19240	1	0	0
T3	9358	2	0	0
T4	17400	2	0	0
T5	16392	1	0	0
T6	16111	1	0	0
T7	20575	2	0	0
T8	11793	2	0	0
T9	23394	8	0	0
T10	23320	8	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670712	9314	0	0
T1	6490	2	0	0
T2	9619	1	0	0
T3	4679	2	0	0
T4	8699	2	0	0
T5	8196	1	0	0
T6	8056	1	0	0
T7	10288	2	0	0
T8	5895	2	0	0
T9	11694	8	0	0
T10	11660	8	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670712	9314	0	0
T1	6490	2	0	0
T2	9619	1	0	0
T3	4679	2	0	0
T4	8699	2	0	0
T5	8196	1	0	0
T6	8056	1	0	0
T7	10288	2	0	0
T8	5895	2	0	0
T9	11694	8	0	0
T10	11660	8	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	9314	0	0
T1	3245	2	0	0
T2	4810	1	0	0
T3	2339	2	0	0
T4	4349	2	0	0
T5	4098	1	0	0
T6	4027	1	0	0
T7	5143	2	0	0
T8	2948	2	0	0
T9	5849	8	0	0
T10	5831	8	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	9314	0	0
T1	3245	2	0	0
T2	4810	1	0	0
T3	2339	2	0	0
T4	4349	2	0	0
T5	4098	1	0	0
T6	4027	1	0	0
T7	5143	2	0	0
T8	2948	2	0	0
T9	5849	8	0	0
T10	5831	8	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670751	9314	0	0
T1	6492	2	0	0
T2	9619	1	0	0
T3	4680	2	0	0
T4	8697	2	0	0
T5	8196	1	0	0
T6	8056	1	0	0
T7	10288	2	0	0
T8	5894	2	0	0
T9	11703	8	0	0
T10	11656	8	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	28670751	9314	0	0
T1	6492	2	0	0
T2	9619	1	0	0
T3	4680	2	0	0
T4	8697	2	0	0
T5	8196	1	0	0
T6	8056	1	0	0
T7	10288	2	0	0
T8	5894	2	0	0
T9	11703	8	0	0
T10	11656	8	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	23292	0	0
T1	13522	6	0	0
T2	20042	16	0	0
T3	9749	2	0	0
T4	18119	6	0	0
T5	17076	21	0	0
T6	16783	20	0	0
T7	21434	2	0	0
T8	12283	6	0	0
T9	24365	8	0	0
T10	24296	8	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	23292	0	0
T1	13522	6	0	0
T2	20042	16	0	0
T3	9749	2	0	0
T4	18119	6	0	0
T5	17076	21	0	0
T6	16783	20	0	0
T7	21434	2	0	0
T8	12283	6	0	0
T9	24365	8	0	0
T10	24296	8	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	23292	0	0
T1	404	6	0	0
T2	599	16	0	0
T3	290	2	0	0
T4	542	6	0	0
T5	510	21	0	0
T6	502	20	0	0
T7	641	2	0	0
T8	368	6	0	0
T9	733	8	0	0
T10	731	8	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	23292	0	0
T1	404	6	0	0
T2	599	16	0	0
T3	290	2	0	0
T4	542	6	0	0
T5	510	21	0	0
T6	502	20	0	0
T7	641	2	0	0
T8	368	6	0	0
T9	733	8	0	0
T10	731	8	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	23292	0	0
T1	13522	6	0	0
T2	20042	16	0	0
T3	9749	2	0	0
T4	18119	6	0	0
T5	17076	21	0	0
T6	16783	20	0	0
T7	21434	2	0	0
T8	12283	6	0	0
T9	24365	8	0	0
T10	24296	8	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	23292	0	0
T1	13522	6	0	0
T2	20042	16	0	0
T3	9749	2	0	0
T4	18119	6	0	0
T5	17076	21	0	0
T6	16783	20	0	0
T7	21434	2	0	0
T8	12283	6	0	0
T9	24365	8	0	0
T10	24296	8	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	7267	0	0
T1	404	1	0	0
T2	599	1	0	0
T3	290	3	0	0
T4	542	1	0	0
T5	510	1	0	0
T6	502	1	0	0
T7	641	19	0	0
T8	368	1	0	0
T9	733	8	0	0
T10	731	8	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	23292	0	0
T1	13522	6	0	0
T2	20042	16	0	0
T3	9749	2	0	0
T4	18119	6	0	0
T5	17076	21	0	0
T6	16783	20	0	0
T7	21434	2	0	0
T8	12283	6	0	0
T9	24365	8	0	0
T10	24296	8	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59730137	23292	0	0
T1	13522	6	0	0
T2	20042	16	0	0
T3	9749	2	0	0
T4	18119	6	0	0
T5	17076	21	0	0
T6	16783	20	0	0
T7	21434	2	0	0
T8	12283	6	0	0
T9	24365	8	0	0
T10	24296	8	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	237	0	0
T14	579	0	0	0
T23	3709	0	0	0
T33	1201	0	0	0
T34	732	0	0	0
T35	464	0	0	0
T36	34109	1	0	0
T37	730	0	0	0
T50	0	1	0	0
T79	243	0	0	0
T90	3320	2	0	0
T96	0	3	0	0
T97	0	1	0	0
T98	735	0	0	0
T107	0	2	0	0
T108	0	1	0	0
T110	0	3	0	0
T130	0	1	0	0
T131	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1809921	9314	0	0
T1	404	2	0	0
T2	599	1	0	0
T3	290	2	0	0
T4	542	2	0	0
T5	510	1	0	0
T6	502	1	0	0
T7	641	2	0	0
T8	368	2	0	0
T9	733	8	0	0
T10	731	8	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	23292	0	0
T1	3245	6	0	0
T2	4810	16	0	0
T3	2339	2	0	0
T4	4349	6	0	0
T5	4098	21	0	0
T6	4027	20	0	0
T7	5143	2	0	0
T8	2948	6	0	0
T9	5849	8	0	0
T10	5831	8	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14335077	23292	0	0
T1	3245	6	0	0
T2	4810	16	0	0
T3	2339	2	0	0
T4	4349	6	0	0
T5	4098	21	0	0
T6	4027	20	0	0
T7	5143	2	0	0
T8	2948	6	0	0
T9	5849	8	0	0
T10	5831	8	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12723547	23292	0	0
T1	3103	6	0	0
T2	3821	16	0	0
T3	2224	2	0	0
T4	3963	6	0	0
T5	2601	21	0	0
T6	2612	20	0	0
T7	5053	2	0	0
T8	2706	6	0	0
T9	5494	8	0	0
T10	5092	8	0	0